General Description
The a6402 MegaCore function implements a universal asynchronous receiver/transmitter (UART), which provides an interface between a microprocessor and a serial communications channel.

Features
*a6402 MegaCore function implementing a universal asynchronous receiver/transmitter (UART)
*Optimized for FLEX® and MAX® architectures
*Uses approximately 162 FLEX logic elements (LEs)
*Programmable word length, stop bits, and parity
*Full duplex operation
*Includes status flags for parity, framing, and overrun errors
*Functionally based on the Harris HD-6402 device, except as noted in the “Variations & Clarifications” section on page 63

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General Description
The a8237 MegaCore function implements a programmable DMA controller, which controls memory-to-peripheral and memory-tomemory data transfers and provides block memory initialization capability. Four independently programmable channels are available in the a8237, and DMA requests can be made via hardware or software. Figure 1 shows the symbol for the a8237

Features
*a8237 MegaCore function implementing a programmable direct memory access (DMA) controller
*Optimized for FLEX® architecture
*Provides four independent channels
*Offers static read/write or handshaking modes
*Includes direct bit set/reset capability
*Uses approximately 1,201 FLEX logic elements (LEs)
*Functionally based on the Intel 8237A and Harris 82C37A devices, except as noted in “Variations & Clarifications” on page 24

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EP220 - Classic EPLDs

Altera 2009/04/15 09:22
General Description
The EPROM-based EP220 and EP224 devices feature a flexible I/O architecture and implement 150 usable (300 available) gates of custom user logic functions. EP220 and EP224 devices can be used as upgrades for high-speed bipolar programmable logic devices (PLDs) or for 74-series LS and CMOS (SSI and MSI) logic devices in high-performance microcomputer systems.
Compared to bipolar devices of equivalent speed, the EP220 and EP224 offer lower power consumption, faster input-to-nonregistered-output delay (tPD) in combinatorial mode, and higher counter frequencies in registered applications. This added performance supports faster state machine designs compared to bipolar devices, and provides additional timing margin for existing designs. The EP220 and EP224 are ideal for high-volume manufacturing of high-performance systems. These devices improve performance and decrease system noise, power consumption, and heat generation.

Features
*High-performance, low-power Erasable Programmable Logic Devices (EPLDs) with 8 macrocells
–Combinatorial speeds as low as 7.5 ns
–Counter frequencies of up to 100 MHz
–Pipelined data rates of up to 115 MHz
–Maximum 5.5-ns Clock-to-output time; minimum 4.5-ns setup time
*Replacement or upgrade for 16V8/20V8 PAL and GAL devices
*Up to 18 inputs (10 dedicated inputs) in EP220, 22 inputs (14 dedicated inputs) in EP224; up to 8 outputs in both EP220 and EP224
*Macrocells independently programmable for both registered and combinatorial logic
*Programmable inversion control supporting active-high or activelow outputs
*Low power consumption
–Typical ICC = 90 mA at 25 MHz (for -7A speed grades)
–Quarter-power mode (ICC = 40 mA)
–Programmable zero-power mode with typical ICC = 50㎂(for -10A and -12 speed grades)
*Programmable Security Bit for total protection of proprietary designs
*Low output skew for Clock driver applications
*100% generically tested to provide 100% programming yield
*Software and programming support from Altera and a wide range of third-party tools
*Available in windowed ceramic and one-time-programmable (OTP) plastic packages
–20-pin plastic J-lead package (PLCC)
–20-pin ceramic and plastic dual in-line packages (CerDIP and PDIP)
–24-pin PDIP
–28-pin PLCC

EP224, EP220-7, EP224-7, EP220-10, EP224-10, EP220-10A, EP224-10A
TAG Classic, EPLDs

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Introduction
The CycloneTM field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phaselocked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements, Cyclone devices are a cost-effective solution for data-path applications. Cyclone devices support various I/O standards, including LVDS at data rates up to 311 megabits per second (Mbps) and 66-MHz, 32-bit peripheral component interconnect (PCI), for interfacing with and supporting ASSP and ASIC devices. Altera also offers new low-cost serial configuration devices to configure Cyclone devices.

Features
*2,910 to 20,060 LEs
*Up to 294,912 RAM bits (36,864 bytes)
*Supports configuration through low-cost serial configuration device
*Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards
*Support for 66-MHz, 32-bit PCI standard
*Low speed (311 Mbps) LVDS I/O support
*Up to two PLLs per device provide clock multiplication and phase shifting
*Up to eight global clock lines with six clock resources available per logic array block (LAB) row
*Support for external memory, including DDR SDRAM (133 MHz), FCRAM, and single data rate (SDR) SDRAM
*Support for multiple intellectual property (IP) cores, including Altera MegaCore functions and Altera Megafunctions Partners Program (AMPPSM) megafunctions

EP1C3F400, EP1C4F400m EP1C6F400, EP1C12F400

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Introduction
The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phaselocked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements, Cyclone devices are a cost-effective solution for data-path applications. Cyclone devices support various I/O standards, including LVDS at data rates up to 640 megabits per second (Mbps), and 66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI), for interfacing with and supporting ASSP and ASIC devices. Altera also offers new low-cost serial configuration devices to configure Cyclone devices.

Functional Description
Cyclone® devices contain a two-dimensional row- and column-based architecture to implement custom logic. Column and row interconnects of varying speeds provide signal interconnects between LABs and embedded memory blocks.
The logic array consists of LABs, with 10 LEs in each LAB. An LE is a small unit of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the device. Cyclone devices range between 2,910 to 20,060 LEs.
M4K RAM blocks are true dual-port memory blocks with 4K bits of memory plus parity (4,608 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 36-bits wide at up to 250 MHz. These blocks are grouped into columns across the device in between certain LABs. Cyclone devices offer between 60 to 288 Kbits of embedded RAM.
Each Cyclone device I/O pin is fed by an I/O element (IOE) located at the ends of LAB rows and columns around the periphery of the device. I/O pins support various single-ended and differential I/O standards, such as the 66- and 33-MHz, 64- and 32-bit PCI standard and the LVDS I/O standard at up to 640 Mbps. Each IOE contains a bidirectional I/O buffer and three registers for registering input, output, and output-enable signals. Dual-purpose DQS, DQ, and DM pins along with delay chains (used to phase-align DDR signals) provide interface support with external memory devices such as DDR SDRAM, and FCRAM devices at up to 133 MHz (266 Mbps).
Cyclone devices provide a global clock network and up to two PLLs. The global clock network consists of eight global clock lines that drive throughout the entire device. The global clock network can provide clocks for all resources within the device, such as IOEs, LEs, and memory blocks. The global clock lines can also be used for control signals. Cyclone PLLs provide general-purpose clocking with clock multiplication and phase shifting as well as external outputs for high-speed differential I/O support.

Features
The Cyclone device family offers the following features:
*2,910 to 20,060 LEs, see Table 1–1
*Up to 294,912 RAM bits (36,864 bytes)
*Supports configuration through low-cost serial configuration device
*Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards
*Support for 66- and 33-MHz, 64- and 32-bit PCI standard
*High-speed (640 Mbps) LVDS I/O support
*Low-speed (311 Mbps) LVDS I/O support
*311-Mbps RSDS I/O support
*Up to two PLLs per device provide clock multiplication and phase shifting
*Up to eight global clock lines with six clock resources available per logic array block (LAB) row
*Support for external memory, including DDR SDRAM (133 MHz), FCRAM, and single data rate (SDR) SDRAM
*Support for multiple intellectual property (IP) cores, including Altera® MegaCore® functions and Altera Megafunctions Partners Program (AMPPSM) megafunctions.

EP1C4, EP1C6, EP1C12, EP1C20

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8B10B - Encoder/Decoder

Altera 2008/10/24 09:38
General Description
Encoders and decoders are used for physical layer coding for Gigabit Ethernet, Fibre Channel, and other applications. The 8b/10b encoder takes byte inputs, and generates a direct current (DC) balanced stream (equal number of 1s and 0s) with a maximum run length of 5. Some of the
individual 10-bit codes will have an equal number of 1s and 0s, while others will have either four 1s and six 0s, or, six 1s and four 0s. In the latter case, the disparity between 1s and 0s is used as an input to the next 10-bit code generation, so that the disparity can be reversed, and maintain an overall balanced stream. For this reason, some 8-bit inputs have two valid 10-bit codes, depending on the input disparity.

Features
*Support for Arria™ GX device family
*8b/10b encoding and decoding
*Cascaded encoding and decoding
*Industry compatible special character coding
*Easy-to-use IP MegaWizard® interface
*Support for OpenCore Plus evaluation
*IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators

TAG Decoder

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General Description
The Stratix II EP2S180 DSP development board provides a hardware platform that designers can use to develop DSP systems based on Stratix II devices. Combined with DSP intellectual property (IP) from Altera and partners in the Altera Megafunction Partners Program (AMPPSM), users can quickly develop powerful DSP systems. Altera’s unique OpenCore® Plus technology allows users to evaluate MegaCore® functions in hardware prior to licensing them.
DSP Builder, version 5.0.1 includes a library for the Stratix II EP2S180 DSP development board. This library allows algorithm development, simulation, and verification on the board, all from within the MathWorks MATLAB/Simulink system-level design tool. Additionally, the Stratix II DSP development board includes a Texas Instrument EVM (crossplatform) daughter card connector, which enables development and verification of FPGA co-processors for off loading and accelerating compute-bound algorithms from programmable DSP processors.

TAG DSP

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General Description
Altera FLEX 10KE devices are enhanced versions of FLEX 10K devices.
Based on reconfigurable CMOS SRAM elements, the FLEX architecture incorporates all features necessary to implement common gate array megafunctions.
With up to 200,000 typical gates, FLEX 10KE devices provide the density, speed, and features to integrate entire systems, including multiple 32-bit buses, into a single device.
The ability to reconfigure FLEX 10KE devices enables 100% testing prior to shipment and allows the designer to focus on simulation and design verification.
FLEX 10KE reconfigurability eliminates inventory management for gate array designs and generation of test vectors for fault coverage.
Table 5 shows FLEX 10KE performance for some common designs.
All performance values were obtained with Synopsys DesignWare or LPM functions.
Special design techniques are not required to implement the applications; the designer simply infers or instantiates a function in a Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or chematic design file.

Features
* Embedded programmable logic devices (PLDs), providing system-on-a-programmable-chip (SOPC) integration in a single device
- Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions
- Dual-port capability with up to 16-bit width per embedded array block (EAB)
- Logic array for general logic functions
* High density
- 30,000 to 200,000 typical gates (see Tables 1 and 2)
- Up to 98,304 RAM bits (4,096 bits per EAB), all of which can be used without reducing logic capacity
* System-level features
- MultiVoltTM I/O pins can drive or be driven by 2.5-V, 3.3-V, or 5.0-V devices
- Low power consumption
- Bidirectional I/O performance (tSU and tCO) up to 212 MHz
- Fully compliant with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz
- -1 speed grade devices are compliant with PCI Local Bus Specification, Revision 2.2, for 5.0-V operation
- Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990, available without consuming additional device logic

EPF10K50E
EPF10K50S
EPF10K100E
EPF10K130E
EPF10K200E

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General Description
The a8251 MegaCore function provides an interface between a microprocessor and a serial communications channel.
The a8251 receives and transmits data in a variety of configurations including 7- or 8-bit data
words, with odd, even, or no parity, and 1 or 2 stop bits. The transmitter and receiver can be designed for synchronous or asynchronous operation.

Features
* a8251 MegaCore function that provides an interface between a microprocessor and a serial communication channel
* Optimized for FLEX® architecture
* Programmable word length, stop bits, and parity
* Offers divide-by-1, -16, or -64 mode
* Supports synchronous and asynchronous operation
* Uses approximately 528 FLEX logic elements (LEs)
* Includes:
– Error detection
– False start bit detection
– Automatic break detection
– Internal and external sync character detection
* Functionally based on the Intel M8251A device, except as noted in the “Variations & Clarifications” on page 44

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General Description
Similar to APEX 20K and APEX 20KE devices, APEX 20KC devices offer the MultiCore architecture, which combines the strengths of LUT-based and product-term-based devices with an enhanced memory structure.
LUT-based logic provides optimized performance and efficiency for datapath, register-intensive, mathematical, or digital signal processing (DSP) designs.
Product-term-based logic is optimized for complex combinatorial paths, such as complex state machines.
LUT- and productterm-based logic combined with memory functions and a wide variety of MegaCore and AMPP functions make the APEX 20KC architecture uniquely suited for SOPC designs.
Applications historically requiring a combination of LUT-, product-term-, and memory-based devices can now be integrated into one APEX 20KC device.
APEX 20KC devices include additional features such as enhanced I/O standard support, CAM, additional global clocks, and enhanced ClockLock clock circuitry.

Features
* Programmable logic device (PLD) manufactured using a 0.15-μm alllayer copper-metal fabrication process
- 25 to 35% faster design performance than APEXTM 20KE devices
- Pin-compatible with APEX 20KE devices
- High-performance, low-power copper interconnect
- MultiCoreTM architecture integrating look-up table (LUT) logic and embedded memory
- LUT logic used for register-intensive functions
- Embedded system blocks (ESBs) used to implement memory functions, including first-in first-out (FIFO) buffers, dual-port RAM, and content-addressable memory (CAM)
* High-density architecture
- 200,000 to 1 million typical gates (see Table 1)
- Up to 38,400 logic elements (LEs)
- Up to 327,680 RAM bits that can be used without reducing available logic

EP20K200C
EP20K400C
EP20K600C
EP20K1000C
TAG device, Logic

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