General Description
ASM8P18xx is a high performance, adjustable frequency, PWM controller with an integrated spread spectrum modulator for EMI reduction. It contains all the functions of a standard PWM controller along with a user configurable spread spectrum modulation with adjustable spread. ASM8P18xx allows significant system cost savings by reducing the number of PCB layers and shielding that are traditionally required to pass EMI regulation.
ASM8P18xx is the industry’s first general purpose EMI reduction IC, specifically designed for use in SMPS systems. ASM8P18xx is compatible to any other 3842 PWM controllers.
ASM8P18xx is capable of driving 1A maximum current output and it covers a wide supply voltage range from 7V DC to 30V DC. The PWM frequency is selectable from 40 KHz to 400 KHz.
ASM8P18xx provides under voltage lockout, thermal shutdown, overload, and undercurrent protection. It is available in 8-pin MicroSO, P-DIP and SOIC package.

Features
*30V maximum operating voltage with CMOS technology
*Adjustable PWM frequencies (40 KHz to 400 KHz)
*Maximum Output drive current of 1A.
*Wide duty cycle range (0% minimum to 95% maximum)
*Spread spectrum modulation with adjustable spread.
*Under voltage lockout with hysteresis.
*Low startup current: 275?A maximum
*Pin compatible with industry standard 3842 PWM controller.
*Temperature range –40°C to +85°C.
*Thermal shutdown, overload and undercurrent protection.
*Frequency skip mode.
*Available in 8-pin plastic MicroSO, P-DIP and SOIC packages.

Applications
*Off-line converter
*DC-DC converter
*Monitor power supply
*Computer/DVD/STB power supply
*Wireless base station power supply
*Telecom power supply

ASM8P18S42ER, ASM8P1843, ASM8P18S43ER, ASM8P18S44ER, ASM8P18S45ER

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General Description
The ASM705 / 706 / 707 / 708 and AS813L are cost effective CMOS supervisor circuits that monitor power-supply and battery voltage level, and μP/μC operation.
The family offers several functional options. Each device generates a reset signal during power-up, power-down and during brownout conditions. A reset is generated when the supply drops below 4.65V (ASM705/707/813L) or 4.40V (ASM706/708). For 3V power supply applications, refer to the ASM705P/R/S/T data sheet. In addition, the ASM705/706/813L feature a 1.6 second watchdog timer. The ASM707/708 have both active-HIGH and active-LOW reset outputs but no watchdog function. The ASM813L has the same pin-out and functions as the ASM705 but has an active-HIGH reset output. A versatile power-fail circuit has a 1.25V threshold, useful in low battery detection and for monitoring non-5V supplies. All devices have a manual reset (MR) input. The watchdog timer output will trigger a reset if connected to MR.
All devices are available in 8-pin DIP, SO and MicroSO packages.

Features
*Precision power supply monitor
-4.65V threshold (ASM705/707/813L)
-4.40V threshold (ASM706/708)
*Debounced manual reset input
*Voltage monitor
-1.25V threshold
-Battery monitor / Auxiliary supply monitor
*Watchdog timer (ASM705/706/813L)
*200ms reset pulse width
*Active HIGH reset output (ASM707/708/813L)
*MicroSO package

Applications
*Computers and embedded controllers
*Portable/Battery-operated systems
*Intelligent instruments
*Wireless communication systems
*PDAs and hendheld equipment
*Automative Systems
*Safety Systems

ASM706, ASM707, ASM708, ASM705CPA, ASM706CPA, ASM707CPA, ASM708CPA

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Product Description
The P278xA is a versatile spread spectrum frequency modulator designed specifically for digital camera and other digital video and imaging applications. The P278xA reduces electromagnetic interference (EMI) at the clock source, which provides system wide reduction of EMI of all clock dependent signals. The P278xA allows significant system cost savings by reducing the number of circuit board layers and shielding that are traditionally required to pass EMI regulations.
The P278xA uses the most efficient and optimized modulation profile approved by the FCC. The P278xA modulates the output of a single PLL in order to “spread” the bandwidth of a synthesized clock and, more importantly, decreases the peak amplitudes of its harmonics. This results in significantly lower system EMI compared to the typical narrow band signal produced by oscillators and most frequency generators. Lowering EMI by increasing a signal’s bandwidth is called spread spectrum clock generation.

Features
*Provides up to 15dB of EMI suppression
*FCC approved method of EMI attenuation
*Generates a 1X, 2X, and 4X low EMI spread spectrum clock of the input frequency
*Input frequency range from 3 to 78MHz
*External loop filter for spread % adjustment
*Spreading ranges from ±0.25% to ±5.0%
*Ultra low cycle-to-cycle jitter
*Zero-cycle slip
*3.3V operating voltage range
*10 mA output drives
*TTL or CMOS compatible outputs
*Ultra-low power CMOS design
*P278XA is available in 8 pin SOIC and TSSOP Packages
*Available for industrial and automotive temperature ranges.

Applications
The P278xA is targeted towards MFP, xDSL, fax modem, set-top box, USB controller, DSC, and embedded systems.

P278XA-08ST, P278XA-08SR, P278XA-08TT, P278XA-08TR
TAG EMI, ic, Reduction

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General Description
The ASM706P/R/S/T/J and ASM708R/S/T/J are cost effective CMOS supervisor circuits that monitor power-supply and battery voltage level, and μP/μC operation.
The family offers several functional options. Each device generates a reset signal during power-up, power-down and during brownout conditions. A reset is generated when the supply drops below 2.63V (ASM706P/R, ASM708R), 2.93V (ASM706S, ASM708S), 3.08V (ASM706T, ASM708T) or 4.00 (ASM706J, ASM708J). In addition, the ASM706P/R/S/T/J feature a 1.6 second watchdog timer. The watchdog timer output will trigger a reset if connected to MR. Floating the WDI input pin disables the watchdog timer.
The ASM708R/S/T/J have both active-HIGH and active-LOW reset outputs but no watchdog function. The ASM706P has the same pin-out and functions as the ASM706R but has an active-
HIGH reset output.
A versatile power-fail circuit, useful in checking battery levels and non-5V supplies, has a 1.25V threshold. All devices have a manual reset input. All devices are available in 8-pin DIP, SO and the compact MicroSO packages. The MicroSO package requires 50% less PC board area than the conventional SO package.

Features
*Precision power supply minotor
-2.63V threshold (ASM706P/R, ASM708R)
-2.93V threshold (ASM706S, ASM708S)
-3.08V threshold (ASM706T, ASM708T)
-New 4.00V threshold (ASM706J , ASM708J)
*Debounced manual reset input
*Auxiliary voltage monitor comparator
-1.25V threshold
-Battery monitor / auxiliary supply monitor
*Watchdog timer (ASM706P/R/S/T/J)
-Watchdog can be disabled by floating WDI
*200ms reset time delay
*Three reset signal options
-Active HIGH: ASM706P
-Active LOW: ASM706R/S/T/J
-Active HIGH and LOW outputs: ASM708R/S/T/J
*DIP, SO and MicroSO packages
*Guaranteed RESET assertion to VCC = 1.1V

Applications
*Computers and embedded controllers
*CTI applications
*Automotive systems
*Portable/Battery-operated systems
*Intelligent instruments
*Wireless communication systems
*PDAs and hand-held equipment
*Safety systems

ASM706PCPA, ASM706PCSA, ASM706PCUA, ASM706PEPA, ASM706PESA

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Functional description
The AS7C513C is a 5V high-performance CMOS 524,288-bit Static Random Access Memory (SRAM) device organized as 32,768 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 12 ns with output enable access times (tOE) of 6 ns are ideal for highperformance applications.
When CE is high, the device enters standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is static, then full standby power is reached (ISB1).
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE) with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output drivers stay in high-impedance mode.
The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O0 through I/O7, and UB controls the higher bits, I/O8 through I/O15.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5 V supply. The AS7C513C is packaged in common industry standard packages.

Features
*Industrial (-40o to 85oC) temperature
*Organization: 32,768 words × 16 bits
*Center power and ground pins for low noise
*High speed
-12 ns address access time
-6 ns output enable access time
*Low power consumption via chip deselect
*Easy memory expansion with CE, OE inputs
*TTL-compatible, three-state I/O
*Upper and Lower byte pin
*JEDEC standard packaging
-44-pin 400 mil SOJ
-44-pin TSOP 2
*ESD protection ≥ 2000 volts

AS7C513C-12JIN, AS7C513C-12TIN
TAG CMOS, SRAM

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Functional description
The AS7C256B is a 5V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device organized as 32,768 words × 8 bits. It is designed for memory applications requiring fast data access at low voltage, including PentiumTM, PowerPCTM, and portable computing. Alliance’s advanced circuit design and process techniques permit 5.0V operation
without sacrificing performance or operating margins.
The device enters standby mode when CE is high. Equal address access and cycle times (tAA, tRC, tWC) of 12 ns with output enable access times (tOE) of 6 ns are ideal for high-performance applications. The chip enable (CE) input permits easy memory expansion with multiple-bank memory organizations.
A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write enable is low, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible. Operation is from a single 5.0±0.5V supply. The AS7C256B is packaged in high volume industry standard packages.

Features
*Industrial (-40o to 85oC) temperature
*Organization: 32,768 words × 8 bits
*High speed
-12 ns address access time
-6 ns output enable access time
*Low power consumption via chip deselect
*One chip select plus one Output Enable pin
*Bidirectional data inputs and outputs
*TTL-compatible
*28-pin JEDEC standard packages
-300 mil SOJ
-8 × 13.4 mm TSOP
-300 mil PDIP
*ESD protection ≥ 2000 volts

AS7C256B-12PIN, AS7C256B-12JIN, AS7C256B-12TIN
TAG CMOS, SRAM

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GENERAL DESCRIPTION
The AS6C62256 is a 262,144-bit low power CMOS static random access memory organized as 32,768 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature.
The AS6C62256 is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application.
The AS6C62256 operates with wide range power supply 2.7 ~ 5.5V

FEATURES
*Access time : 55ns
*Low power consumption:
- Operation current : 15mA (TYP.), VCC = 3.0V
- Standby current : 1μA (TYP.), VCC = 3.0V
*Wide range power supply : 2.7 ~ 5.5V
*Fully Compatible with all Competitors 5V product
*Fully Compatible with all Competitors 3.3V product
*Fully static operation
*Tri-state output
*Data retention voltage : 2.0V (MIN.)
*All products ROHS Compliant
*Package : 28-pin 600 mil PDIP, 28-pin 330 mil SOP, 28-pin 8mm x 13.4mm sTSOP

AS6C62256-55PCN, AS6C62256-55SCN, AS6C62256-55SIN, AS6C62256-55STCN
AS6C62256-55STIN
TAG CMOS, low, SRAM

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GENERAL DESCRIPTION
The AS6C6264 is a 65,536-bit low power CMOS static random access memory organized as 8,192 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature.
The AS6C6264 is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application.
The AS6C6264 operates with wide range power supply.

FEATURES
*Access time :55ns
*Low power consumption:
- Operation current : 15mA (TYP.), VCC = 3.0V
- Standby current : 1μA (TYP.), VCC = 3.0V
*Wide range power supply : 2.7 ~ 5.5V
*Fully Compatible with all Competitors 5V product
*Fully Compatible with all Competitors 3.3V product
*Fully static operation
*Tri-state output
*Data retention voltage : 2.0V (MIN.)
*All products ROHS Compliant
*Package : 28-pin 600 mil PDIP, 28-pin 330 mil SOP, 28-pin 8mm x 13.4mm sTSOP

AS6C6264-55PCN, AS6C6264-55SCN, AS6C6264-55SIN, AS6C6264-55STCN, AS6C6264-55STIN
TAG CMOS, SRAM

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GENERAL DESCRIPTION
The AS6C4008 is a 4,194,304-bit low power CMOS static random access memory organized as
524,288 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature.
The AS6C4008 is well designed for very low power system applications, and particularly well suited for battery back-up non -volatile memory application.
The AS6C4008 operates from a single power supply of 2.7V ~ 5.5V.

FEATURES
*Access time : 55 ns
*Low power consumption:
*Operatingcurrent : 30/20mA (TYP.)
*Standby current : 4μA (TYP.) C-version
*Single 2.7V ~ 5.5V power supply
*Fully static operation
*Tri-state output
*Data retention voltage : 2.0V (MIN.)
*All products ROHS Compliant
*Package :
32-pin 450 mil SOP
32-pin 8mm x 20mm TSOP-I
32-p:in 600 mil P-DIP
Fully Compatible with all Competitors 5V product
Fully Compatible with all Competitors 3.3V product
32-pin 8mm x 13.4mm sTSOP
36-ball 6mm x 8mm TFBGA
44-pin 8mm x 20mm TSOP-II
TAG CMOS, SRAM

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Functional description
The AS4LC8M8S0 and AS4LC4M16S0 are high-performance 64-megabit CMOS Synchronous Dynamic Random Access Memory (SDRAM) devices organized as 2,097,152 words × 8 bits × 4 banks, and 1,048,576 words × 16 bits × 4 banks, respectively.
Very high bandwidth is achieved using a pipelined architecture where all inputs and outputs are referenced to the rising edge of a common clock.
Programmable burst mode can be used to read up to a full page of data without selecting a
new column address.
The four internal banks can be alternately accessed (read or write) at the maximum clock frequency for seamless interleaving operations.
This provides a significant advantage over asynchronous EDO and fast page mode devices.
This SDRAM product also features a programmable mode register, allowing users to select read latency as well as burst length and type (sequential or interleaved).
Lower latency improves first data access in terms of CLK cycles, while higher latency improves maximum frequency of operation.
This feature enables flexible performance optimization for a variety of applications.

Features
*PC100/133 compliant
*Organization
-2,097,152 words × 8 bits × 4 banks (8M×8)
-1,048,576 words × 16 bits × 4 banks (4M×16)
*Fully synchronous
-All signals referenced to positive edge of clock
*Four internal banks controlled by BA0/BA1 (bank select)
*High speed
-133/125/100 MHz
-5.4 ns (133 MHz)/6 ns (125/100 MHz) clock access time
*Low power consumption
-Standby: 7.2 mW max, CMOS I/O
*4096 refresh cycles, 64 ms refresh interval
*Auto refresh and self refresh
*Automatic and direct precharge
*Burst read, single write operation
*Can assert random column address in every cycle
*LVTTL compatible I/O
*3.3V power supply
*JEDEC standard package, pinout and function
-400 mil, 54-pin TSOP II
*Read/write data masking
*Programmable burst length (1/2/4/8/full page)
*Programmable burst sequence (sequential/interleaved)
*Programmable CAS latency (2/3)

AS4LC8M8S0-75TC
AS4LC4M16S0-75TC
TAG DRAM

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