General Description
The A63L06361 is a high-speed SRAM containing 36M bits of bit synchronous memory, organized as 1024K words by 36 bits.
The A63L06361 combines advanced synchronous peripheral circuitry, 2-bit burst control, input registers, output buffer and a 1M X 36 SRAM core to provide a wide range of data RAM applications.
The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers. Synchronous inputs include all addresses (A0 - A19), all data inputs (I/O1 - I/O36 ), active LOW chip enable ( CE ), two additional chip enables (CE2, CE2 ), burst control inputs ( ADSC , ADSP , ADV ), byte write enables (BWE , BW1 , BW2 , BW3 , BW4 ) and Global Write (GW ). Asynchronous inputs include output enable ( OE ), clock (CLK), BURST mode (MODE) and SLEEP mode (ZZ).
Burst operations can be initiated with either the address status processor ( ADSP ) or address status controller ( ADSC ) input pin. Subsequent burst sequence burst addresses can be internally generated by the A63L06361 and controlled by the burst advance ( ADV ) pin. Write cycles are internally self-timed and synchronous with the rising edge of the clock (CLK).
This feature simplifies the write interface. Individual Byte enables allow individual bytes to be written. BW1 controls I/O1 - I/O9, BW2 controls I/O10 - I/O18, BW3 controls I/O19 - I/O27, and BW4 controls I/O28 - I/O36, all on the condition that BWE is LOW. GW LOW causes all bytes to be written.

Features
*Fast access times: 6.5/7.5/8.0 ns(153/133/117 MHz)
*Single 3.3V±5% power supply
*Synchronous burst function
*Individual Byte Write control and Global Write
*Three separate chip enables allow wide range of options for CE control, address pipelining
*Selectable BURST mode
*SLEEP mode (ZZ pin) provided
*Available in 100-pin LQFP package
*Industrial operating temperature range: -45°C to +125°C for -I series

A63L06361E-6.5, A63L06361E-6.5F, A63L06361E-7.5, A63L06361E-7.5F

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General Description
The LP62S4096E-T is a low operating current 4,194,304-bit static random access memory organized as 524,288 words by 8 bits and operates on a low power supply range: 2.7V to 3.3V. It is built using AMIC's high performance CMOS process.
Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures.
Two chip enable inputs are provided for POWER-DOWN and device enable and an output enable input is included for easy interfacing.
Data retention is guaranteed at a power supply voltage as low as 2V.
*CE2 pin for CSP package only

Features
*Power supply range: 2.7V to 3.6V
*Access times: 55ns / 70ns (max.)
*Current: Very low power version: Operating: 30mA (max.), Standby: 10mA (max.)
*Full static operation, no clock or refreshing required
*All inputs and outputs are directly TTL-compatible
*Common I/O using three-state output
*Data retention voltage: 2V (min.)
*Available in 32-pin TSOP/TSSOP 36-ball CSP package

LP62S4096EV-55LLT, LP62S4096EX-55LLT, LP62S4096EU-55LLT

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General Description
A7121 is a monolithic CMOS integrated circuit for wireless applications in 2.4GHz ISM band. The device is provided in a 32-lead plastic QFN5X5 packaging and is designed as a complete GFSK transceiver up to 3Mbps data rate. The chip features a fully programmable frequency synthesizer with integrated VCO circuitry.

Features
*2400MHz~2484MHz worldwide license free frequency band
*Up to 79 selectable channels
*2.2 V – 2.8 V voltage supply
*Programmable output power up to 0dBm
*Channel switching time < 200us
*1 or 3Mbps high speed data rate
*-20 ºC to 85 ºC operating temperature
*-87dBm sensitivity
*Direct / FIFO mode operation
*Modem interface for low speed, low cost microcontroller
*Low IF architecture with few external components

Typical Applications
*Wireless digital audio
*Wireless Mouse and Keyboard
*2.4GHz ISM Band Communication System
*Wireless game pad
*Wireless toy

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General Description
The A29L320A is a 32Mbit, 3.3 volt-only Flash memory organized as 2,097,152 words of 16 bits or 4,194,304 bytes of 8 bits each. The 8 bits of data appear on I/O0 - I/O7; the 16 bits of data appear on I/O0~I/O15. The A29L320A is offered in 48-ball TFBGA and 48-Pin TSOP packages. This device is designed to be programmed in-system with the standard system 3.3 volt VCC supply. Additional 12.0 volt VPP is not required for in-system write or erase operations. However, the A29L320A can also be programmed in standard EPROM programmers.
The A29L320A has the first toggle bit, I/O6, which indicates whether an Embedded Program or Erase is in progress, or it is in the Erase Suspend. Besides the I/O6 toggle bit, the A29L320A has a second toggle bit, I/O2, to indicate whether the addressed sector is being selected for erase. The A29L320A also offers the ability to program in the Erase Suspend mode. The standard A29L320A offers access times of 70,80,90 and 120ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable ( CE ), write enable (WE ) and output enable (OE ) controls.
The device requires only a single 3.3 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.
The A29L320A is entirely software command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.
Device programming occurs by writing the proper program command sequence. This initiates the Embedded Program algorithm - an internal algorithm that automatically times the program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase command sequence. This initiates the Embedded Erase algorithm - an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper erase margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four.
The host system can detect whether a program or erase operation is complete by observing the RY / BY pin, or by reading the I/O7 (Data Polling) and I/O6 (toggle) status bits.
After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The A29L320A is fully erased when shipped from the factory.
The hardware sector protection feature disables operations for both program and erase in any combination of the sectors of memory. This can be achieved via programming equipment.
The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any other sector that is not selected for erasure. True background erase can thus be achieved.
The hardware RESET pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.

Features
*Single power supply operation
-Regulated voltage range: 2.7 to 3.6 volt read and write operations for compatibility with high performance 3 volt microprocessors
*Access times:
-70/80/90/120 (max.)
*Current:
-2mA active read current at 1MHz
-10mA active read current at 5MHz
-20 mA typical program/erase current
-500 nA typical CMOS standby or Automatic Sleep Mode current
*Flexible sector architecture
-Eight 8 Kbyte sectors
-Sixty-three 64 kbyte sectors
-Any combination of sectors can be erased
-Supports full chip erase
-Sector protection:
*Unlock Bypass Program Command
-Reduces overall programming time when issuing multiple program command sequence
*Top or bottom boot block configurations available
*Embedded Algorithms
-Embedded Erase algorithm will automatically erase the entire chip or any combination of designated sectors and verify the erased sectors
-Embedded Program algorithm automatically writes and verifies data at specified addresses
*Typical 100,000 program/erase cycles per sector
*20-year data retention at 125°C
-Reliable operation for the life of the system
*CFI (Common Flash Interface) compliant
-Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices
*Compatible with JEDEC-standards
-Pinout and software compatible with single-power-supply Flash memory standard
-Superior inadvertent write protection
*Data Polling and toggle bits
-Provides a software method of detecting completion of program or erase operations
*Ready / BUSY pin (RY / BY)
-Provides a hardware method of detecting completion of program or erase operations
*Erase Suspend/Erase Resume
-Suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operation
*Hardware reset pin (RESET )
-Hardware method to reset the device to reading array data
*WP /ACC input pin
-Write protect ( WP ) function allows protection of two outermost boot sectors, regardless of sector protect status
-Acceleration (ACC) function provides accelerated program times
*Hardware/Software temporary sector block unprotect command allows code changes in previously locked sectors
*Hardware/Software sector protect/unprotect command
*Package options
-48-pin TSOP (I) or 48-ball TFBGA
-All Pb-free (Lead-free) products are RoHS compliant

A29L320ATV-70, A29L320ATV-70U, A29L320ATV-70I, A29L320ATV-70F

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General Description
The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process.
The A67L16181, A67L06361 SRAMs integrate a 2M X 18, 1M X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during Write-Read alternation. The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers. The synchronous inputs include all address, all data inputs, active low chip enable (CE), two additional chip enables for easy depth expansion (CE2, CE2 ), cycle start input (ADV/LD ), synchronous clock enable ( CEN ), byte write enables (BW1,BW2,BW3,BW4) and read/write (R/W).
Asynchronous inputs include the output enable (OE), clock (CLK), SLEEP mode (ZZ, tied LOW if unused) and burst mode (MODE). Burst Mode can provide either interleaved or linear operation, burst operation can be initiated by synchronous address Advance/Load (ADV/LD ) pin in Low state. Subsequent burst address can be internally generated by the chip and controlled by the same input pin ADV/LD in High state.
Write cycles are internally self-time and synchronous with the rising edge of the clock input and when R/W is Low. The feature simplified the write interface. Individual Byte enables allow individual bytes to be written. BW1 controls I/Oa pins; BW2 controls I/Ob pins; BW3 controls I/Oc pins; and BW4 controls I/Od pins. Cycle types can only be defined when an address is loaded.
The SRAM operates from a +3.3V power supply, and all inputs and outputs are LVTTL-compatible. The device is ideally suited for high bandwidth utilization systems.

Features
*Fast access time: 6.5/7.5/8.5 ns (153, 133, 117 MHz)
*Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization
*Signal +3.3V ± 5% power supply
*Individual Byte Write control capability
*Clock enable ( CEN) pin to enable clock and suspend operations
*Clock-controlled and registered address, data and control signals
*Registered output for pipelined applications
*Three separate chip enables allow wide range of options for CE control, address pipelining
*Internally self-timed write cycle
*Selectable BURST mode (Linear or Interleaved)
*SLEEP mode (ZZ pin) provided
*Available in 100 pin LQFP package

A67L06361, A67L16181E-6.5, A67L16181E-7.5, A67L16181-8.5

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General Description
The A29L160 is a 16Mbit, 3.0 volt-only Flash memory organized as 2,097,152 bytes of 8 bits or 1,048,576 words of 16 bits each. The 8 bits of data appear on I/O0 - I/O7; the 16 bits of data appear on I/O0~I/O15. The A29L160 is offered in 48-ball FBGA, 44-pin SOP and 48-Pin TSOP packages. This device is designed to be programmed in-system with the standard system 3.0 volt VCC supply. Additional 12.0 volt VPP is not required for in-system write or erase operations. However, the A29L160 can also be programmed in standard EPROM programmers.
The A29L160 has the first toggle bit, I/O6, which indicates whether an Embedded Program or Erase is in progress, or it is in the Erase Suspend. Besides the I/O6 toggle bit, the A29L160 has a second toggle bit, I/O2, to indicate whether the addressed sector is being selected for erase. The A29L160 also offers the ability to program in the Erase Suspend mode. The standard A29L160 offers access times of 70, 90 and 120ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE ) and output enable (OE ) controls.
The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.
The A29L160 is entirely software command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the
erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.
Device programming occurs by writing the proper program command sequence. This initiates the Embedded Program algorithm - an internal algorithm that automatically times the program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase command sequence. This initiates the Embedded Erase algorithm - an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper erase margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four.
The host system can detect whether a program or erase operation is complete by observing the RY / BY pin, or by reading the I/O7 (Data Polling) and I/O6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The A29L160 is fully erased when shipped from the factory. The hardware sector protection feature disables operations
for both program and erase in any combination of the sectors of memory. This can be achieved via programming equipment.
The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any other sector that is not selected for
erasure. True background erase can thus be achieved. The hardware RESET pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.

Features
*Single power supply operation
- Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications
- Regulated voltage range: 3.0 to 3.6 volt read and write operations for compatibility with high performance 3.3 volt microprocessors
*Access times:
- 70/90/120 (max.)
*Current:
- 9 mA typical active read current
- 20 mA typical program/erase current
- 200 nA typical CMOS standby
- 200 nA Automatic Sleep Mode current
*Flexible sector architecture
- 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX31 sectors
- 8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX31 sectors
- Any combination of sectors can be erased
- Supports full chip erase
- Sector protection:
A hardware method of protecting sectors to prevent any inadvertent program or erase operations within that sector. Temporary Sector Unprotect feature allows code changes in previously locked sectors
*Unlock Bypass Program Command
- Reduces overall programming time when issuing multiple program command sequence
*Top or bottom boot block configurations available
*Embedded Algorithms
- Embedded Erase algorithm will automatically erase the entire chip or any combination of designated sectors and verify the erased sectors
- Embedded Program algorithm automatically writes and verifies data at specified addresses
*Typical 100,000 program/erase cycles per sector
*20-year data retention at 125°C
- Reliable operation for the life of the system
*CFI (Common Flash Interface) compliant
- Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices
*Compatible with JEDEC-standards
- Pinout and software compatible with single-power-supply Flash memory standard
- Superior inadvertent write protection
*Data Polling and toggle bits
- Provides a software method of detecting completion of program or erase operations
*Ready / BUSY pin (RY / BY)
- Provides a hardware method of detecting completion of program or erase operations (not available on 44-pin SOP)
*Erase Suspend/Erase Resume
- Suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operation
*Hardware reset pin (RESET )
- Hardware method to reset the device to reading array data
*Package options
- 44-pin SOP or 48-pin TSOP (I) or 48-ball TFBGA
- All Pb-free (Lead-free) products are RoHS compliant

A29L160TM-70, A29L160TV-70, A29L160TV-70F, A29L160TG-70, A29L160TM-90, A29L160TV-90, A29L160TG-90, A29L160TM-120, A29L160TV-120, A29L160TG-120

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GENERAL DESCRIPTION
The A25L016 is 16M bit Serial Flash Memory, with advanced write protection mechanisms,  ccessed by a high speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction.
The memory is organized as 32 blocks, each containing 16 sectors. Each sector is composed of 16 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 8,192 pages, or 2,097,152 bytes.
The whole memory can be erased using the Chip Erase instruction, a block at a time, using Block Erase instruction, or a sector at a time, using the Sector Erase instruction.

FEATURES
*Family of Serial Flash Memories
- A25L016: 16M-bit /2M-byte
*Flexible Sector Architecture with 4KB sectors
- Sector Erase (4K-bytes) in 60ms (typical)
- Block Erase (64K-bytes) in 0.5s (typical)
*Page Program (up to 256 Bytes) in 0.8ms (typical)
*2.7 to 3.6V Single Supply Voltage
*Dual input / output instructions resulting in an equivalent lock frequency of 200MHz:
- Dual Output Fast Read Instruction
- Dual Input and Output Fast Read Instruction
*SPI Bus Compatible Serial Interface
*100MHz Clock Rate (maximum)
*Deep Power-down Mode 5μA (Max)
*16Mbit Flash memory
- Uniform 4-Kbyte sectors
- Uniform 64-Kbyte blocks
*Electronic Signatures
- JEDEC Standard Two-Byte Signature A25L016: (3015h)
- RES Instruction, One-Byte, Signature, for backward compatibility A25L016 (14h)
*Package options
- 8-pin SOP (209mil), 16-pin SOP (300mil), 8-pin DIP (300mil)
- All Pb-free (Lead-free) products are RoHS compliant

A25L016-F, A25L016-UF, A25L016M-F, A25L016M-UF, A25L016N-F, A25L016N-UF

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General Description
The A62S8316 is a low operating current 4,194,304-bit static random access memory organized as 262,144 words by 16 bits and operates on low power supply voltage from 2.7V to 3.6V.
It is built using AMIC’s high performance CMOS process.
Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures.
The chip enable input is provided for POWER-DOWN, device enable.
Two byte enable inputs and an output enable input are included for easy interfacing.
Data retention is guaranteed at a power supply voltage as low as 2V.

Features
*Operating voltage: 2.7V to 3.6V
*Access times: 70 ns (max.)
*Current:
A62S8316-S series; Operating: 50mA (max.)
Standby: 10mA (max.)
A62S8316-SI series: Operating: 50mA (max.)
Standby: 15mA (max.)
*Extended operating temperature range : -25°C to 85°C for -SI series
*Full static operation, no clock or refreshing required
*All inputs and outputs are directly TTL-compatible
*Commo*I/O using three-state output
*Data retentio*voltage: 2V (min.)
*Available i*44-pi*TSOP and 48-ball Mini BGA (6X8) packages.


A62S8316V-70S
A62S8316V-70SI
A62S8316G-70S
TAG CMOS, SRAM

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GENERAL DESCRIPTION
The A25L16P is a 16 Mbit (2M x 8) Serial Flash Memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction.
The memory is organized as 32 sectors, each containing 256 pages.
Each page is 256 bytes wide.
Thus, the whole memory can be viewed as consisting of 8192 pages, or 2,097,152 bytes.
The whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the Sector Erase instruction.

FEATURES
* 16 Mbit of Flash Memory
* Flexible Sector Architecture (4/4/8/16/32)KB/64x31 KB
* Bulk Erase (16 Mbit) in 20s (typical)
* Sector Erase (512 Kbit) in 1s (typical)
* Page Program (up to 256 Bytes) in 1.5ms (typical)
* 2.7 to 3.6V Single Supply Voltage
* SPI Bus Compatible Serial Interface
* 85MHz Clock Rate (maximum)
* Fast Read Dual Operation Instruction (3Bh/BBh)
* Deep Power-down Mode 1μA (typical)
* Top or Bottom Boot Block Configuration Available
* Electronic Signature
- JEDEC Standard Two-Byte Signature (2015h, Bottom;or 2025, Top)
- RES Instruction, One-Byte, Signature (14h)
* Package Options
- 8-pin SOP (209mil), 16-pin SOP, or 8-pin QFN
- All Pb-free (Lead-free) products are ROHS complaint

A2505PM-F
A2540PM-F
A2580PM-F
A2516PM-F
TAG Flash, Memory

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GENERAL DESCRIPTION
The A25L20P/A25L10P/A25L05P are 2M/1M/512 bit Serial Flash Memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction.
The memory is organized as 4/2/1 sectors, each containing 256 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 1024/512/256 pages, or 262,144/131,072/65,536 bytes.
The whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the Sector Erase instruction.

FEATURES
* 2Mbit / 1Mbit / 512Kbit of Flash Memory
* Flexible Sector Architecture
- 25L20P: (4/4/8/16/32)KB/64x3 KB
- 25L10P: (4/4/8/16/32)KB/64x1KB
- 25L05P: (4/4/8/16/32)KB
* Bulk Erase (typical)
- 25L20P (2M) in 6s
- A25L10P (1M) in 4s
- A25L05P (512K) in 3s
* Sector Erase (512 Kbit) in 1s (typical)
* Page Program (up to 256 Bytes) in 3ms (typical)
* 2.7 to 3.6V Single Supply Voltage
* SPI Bus Compatible Serial Interface
* 85MHz Clock Rate (maximum)
* Deep Power-down Mode 1μA (typical)
* Top or Bottom boot block configuration available
* Electronic Signatures
- JEDEC Standard Two-Byte Signature
A25L20P: (2012h, Bottom) or (2022h, top)
A25L10P: (2011h, Bottom) or (2021h, top)
A25L05P: (2010h, Bottom) or (2020h, top)
- RES Instruction, One-Byte, Signature, for backward compatibility
A25L20P (11h)
A25L10P (10h)
A25L05P (05h)
* Package options
- 8-pin SOP (150mil or 209mil), 8-pin DIP (300mil) or 8-pin QFN
- All Pb-free (Lead-free) products are RoHS compliant

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