DISTINCTIVE CHARACTERISTICS
■ 32 words sequential with wrap around (linear 32), bottom boot
■ One 8 Kword, two 4 Kword, one 48 Kword, three 64 Kword, and two 128 Kword sectors
■ Single power supply operation
— Regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessors
■ Read access times
Burst access times as fast as 17 ns at industrial temperature range (18 ns at extended temperature range) Initial/random access times as fast as 65 ns
■ Alterable burst length via BAA# pin
■ Power dissipation (typical)
— Burst Mode Read: 15 mA @ 25 MHz, 20 mA @ 33 MHz, 25 mA @ 40 MHz
— Program/Erase: 20 mA
— Standby mode, CMOS: 3 µA
■ 5 V-tolerant data, address, and control signals
■ Sector Protection
— Implemented using in-system or via programming equipment
— Temporary Sector Unprotect feature allows code changes in previously locked sectors
■ Unlock Bypass Program Command
— Reduces overall programming time when issuing multiple program command sequences
■ Embedded Algorithms
— Embedded Erase algorithm automatically preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically writes and verifies data at specified addresses
■ Minimum 100,000 erase cycle guarantee per sector
■ 20-year data retention
■ Compatibility with JEDEC standards
— Pinout and software compatible with singlepower supply Flash
— Superior inadvertent write protection
— Backward-compatible with AMD Am29LV and
Am29F flash memories: powers up in asynchronous mode for system boot, but can immediately be placed into burst mode
■ Data# Polling and toggle bits
— Provides a software method of detecting program or erase operation completion
■ Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting program or erase cycle completion
■ Erase Suspend/Erase Resume
— Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation
■ Hardware reset pin (RESET#)
— Hardware method to reset the device for reading array data
■ Package Option
— 56-pin SSOP

GENERAL DESCRIPTION
 The Am29BL802C is an 8 Mbit, 3.0 Volt-only burst mode Flash memory devices organized as 524, 288 words. The device is offered in a 56-pin SSOP package. These devices are designed to be programmed in-system with the standard system 3.0-volt VCC supply. A 12.0-volt VPP or 5.0 VCC is not required for program or erase operations. The device can also be programmed in standard EPROM programmers.
 The device offers access times of 65, 70, 90, and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

Burst Mode Features
The Am29BL802C offers a Linear Burst mode—a 32 word sequential burst with wrap around—in a bottom boot configuration only. This devices require additional control pins for burst operations: Load Burst Address (LBA#), Burst Address Advance (BAA#), and Clock (CLK). This implementation allows easy interface with minimal glue logic to a wide range of microprocessors/microcontrollers for high performance read operations.

AMD Flash Memory Features
 Each device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The I/O and control signals are 5V tolerant.
 The Am29BL802C is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading
from other Flash or EPROM devices.
 Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.
 The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.
 The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment.
 The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved.
 The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.
 The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.
AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.

AM29BL802CB-65RZI
AM29BL802CB-70RZI
AM29BL802CB-90RZI
AM29BL802CB-120RZI
AM29BL802CB-65RZE
AM29BL802CB-70RZE
AM29BL802CB-90RZE
AM29BL802CB-120RZE
AM29BL802CB-65RZF
AM29BL802CB-70RZF
AM29BL802CB-90RZF
AM29BL802CB-120RZF
AM29BL802CB-65RZK
AM29BL802CB-70RZK
AM29BL802CB-90RZK
AM29BL802CB-120RZK

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DISTINCTIVE CHARACTERISTICS
* Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications
— Regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with
high performance 3.3 volt microprocessors
* Manufactured on 0.35 mm process technology
— Compatible with 0.5 mm Am29LV400 device
* High performance
— Full voltage range: access times as fast as 80 ns
— Regulated voltage range: access times as fast as 70 ns
* Ultra low power consumption (typical values at 5 MHz)
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 7 mA read current
— 15 mA program/erase current
* Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and seven 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and seven 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to prevent any program or erase operations within
that sector Sectors can be locked in-system or via programming equipment Temporary Sector Unprotect feature allows code changes in previously locked sectors
* Unlock Bypass Program Command
— Reduces overall programming time when issuing multiple program command sequences
* Top or bottom boot block configurations available
* Embedded Algorithms
— Embedded Erase algorithm automatically preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically writes and verifies data at specified addresses
* Minimum 1,000,000 write cycle guarantee per sector
* Package option
— 48-ball FBGA
— 48-pin TSOP
— 44-pin SO
* Compatibility with JEDEC standards
— Pinout and software compatible with singlepower supply Flash
— Superior inadvertent write protection
* Data# Polling and toggle bits
— Provides a software method of detecting program or erase operation completion
* Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting program or erase cycle completion
* Erase Suspend/Erase Resume
— Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation
* Hardware reset pin (RESET#)
— Hardware method to reset the device to reading array data

GENERAL DESCRIPTION
 The Am29LV400B is a 4 Mbit, 3.0 volt-only Flash memory organized as 524,288 bytes or 262,144 words. The device is offered in 48-ball FBGA, 44-pin SO, and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed in-system using only a single 3.0 volt VCC supply. No VPP is required for write or erase operations. The device can also be programmed in standard EPROM programmers.

 This device is manufactured using AMD’s 0.35 mm process technology, and offers all the features and benefits of the Am29LV400, which was manufactured using 0.5 mm process technology. In addition, the Am29LV400B features unlock bypass programming and in-system sector protection/unprotection.
The standard device offers access times of 70, 80, 90 and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

 The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.
The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

 Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence.
 This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.

 The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory.
This can be achieved in-system or via programming equipment.

 The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.

 AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.

AM29LV400B Am29LV400BT70REC Am29LV400BB70REC Am29LV400BT80EC   
Am29LV400BB80EC Am29LV400BT90EC Am29LV400BB90EC Am29LV400BT120EC   
Am29LV400BB120EC Am29LV400BT70RFC Am29LV400BB70RFC Am29LV400BT80FC   
Am29LV400BB80FC Am29LV400BT90FC Am29LV400BB90FC

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DISTINCTIVE CHARACTERISTICS
* Pin/function compatible with Emulex FAS216/236
* AMD’s Patented programmable GLITCH EATERTM Circuitry on REQ and ACK inputs
* 10 Mbytes/s synchronous Fast SCSI transfer rate
* 20 Mbytes/s DMA transfer rate
* 16-Bit DMA interface plus 2 bits of parity
* Flexible three bus architecture
* Single-ended SCSI bus supported by Am53CF94
* Differential SCSI bus supported by Am53CF96
* Selection of multiplexed or non-multiplexed address and data bus
* High current drivers (48 mA) for direct connection to the single-ended SCSI bus
* Supports Disconnect and Reselect commands
* Supports burst mode DMA operation with a threshold of eight
* Supports 3-byte tagged-queueing as per the SCSI-2 specification
* Supports group 2 and 5 command recognition as per the SCSI-2 specification
* Advanced CMOS process for lower power consumption
* AMD’s exclusive programmable power-down feature
* 24-Bit extended transfer counter allows for data block transfer of up to 16 Mbytes
* Independently programmable 3-byte message and group 2 identification
* Additional check for ID message during bus-initiated Select with ATN
* Reselection has QTAG features of ATN3
* Access FIFO Command
* Delayed enable signal for differential drivers avoid contention on SCSI differential lines
* Programmable Active Negation on REQ, ACK and Data lines
* Register programmable control of assertion/ deassertion delay for REQ and ACK lines
* Part-unique ID code
* Am53CF94 available in 84-pin PLCC package
* Am53CF96 available in 100-pin PQFP package
* Am53CF94 available in 3.3 V version
* Supports clock operating frequencies from 10 MHz–40 MHz
* Supports Scatter-Gather or Back-to-Back synchronous data transfers

GENERAL DESCRIPTION
 The Enhanced SCSI-2 Controller (ESC) was designed to support Fast SCSI-2 transfer rates of up to 10 Mbytes/s in synchronous mode and up to 7 Mbytes/s in the asynchronous mode. The ESC is downward compatible with the Am53C94/96, combining its functionality with features such as Fast SCSI, programmable Active Negation, a 24-bit transfer counter, and a part-unique ID code containing manufacturer and serial # information.
 AMD’s proprietary features such as power-down mode for SCSI transceivers, programmable GLITCH EATER, and extended Target command set are also included for improved product performance.

 The Enhanced SCSI-2 Controller (ESC) has a flexible three bus architecture. The ESC has a 16-bit DMA interface, an 8-bit host data interface and an 8-bit SCSI data interface. The ESC is designed to minimize host intervention by implementing common SCSI sequences in hardware. An on-chip state machine reduces protocol overheads by performing the required sequences in response to a single command from the host. Selection,  reselection, information transfer and disconnection commands are directly supported.

 The 16-byte-internal FIFO further assists in minimizing host involvement. The FIFO provides a temporary storage for all command, data, status and message bytes as they are transferred between the 16-bit host data bus and the 8-bit SCSI data bus. During DMA operations the FIFO acts as a buffer to allow greater latency in the DMA channel. This permits the DMA channel to be suspended for higher priority operations such as DRAM refresh or reception of an ISDN packet.

 Parity on the DMA bus is optional. Parity can either be generated and checked or it can be simply passed through.

 The Target command set for the Am53CF94/96 includes an additional command, the Access FIFO command, to allow the host or DMA controller to remove remaining FIFO data following the host’s issuance of a Target abort DMA command or following an abort due to parity error. This command facilitates data recovery and thereby minimizes the need to re-transmit data. AMD’s exclusive power-down feature can be enabled to help reduce power consumption during the chip’s sleep mode. The receivers on the SCSI bus may be turned off to eliminate current that may flow because termination power (~3 V) is close to the trip point of the input buffers.

 The patented GLITCH EATER Circuitry in the Enhanced SCSI-2 Controller can be programmed to filter glitches with widths up to 35 ns. It is designed to dramatically increase system reliability by detecting and removing glitches that may cause system failure. The GLITCH EATER Circuitry is implemented on the ACK and REQ lines since they are most susceptible to electrical anomalies such as reflections and voltage spikes. Such signal inconsistencies can trigger false REQ/ACK handshaking, false data transfers, addition of random data, and double clocking. AMD’s GLITCH EATER Circuitry therefore maintains system performance and improves reliability. The following diagram illustrates this circuit’s operation.

The Am53CF94 is also available in a 3.3 V version.

AM53CF96 AM53CF96JC AM53CF96KC AM53CF96JC/W AM53CF96KC/W AM53CF94JC
AM53CF94KC AM53CF94JC/W AM53CF94KC/W


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GENERAL DESCRIPTION
The PALCE16V8 is an advanced PAL device built with low-power, high-speed,
electrically-erasable CMOS technology. It is functionally compatible with all 20-pin GAL devices. The macrocells provide a universal device architecture. The PALCE16V8 will directly replace the PAL16R8 and PAL10H8 series devices, with the exception of the PAL16C1.
 The PALCE16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic can always be reduced to sum-of-products form, taking advantage of the very wide input gates available in PAL devices. The equations are programmed into the device through floatinggate
cells in the AND logic array that can be erased electrically.
 The fixed OR array allows up to eight data product terms per output for logic functions. The sum of these products feeds the output macrocell. Each macrocell can be programmed as registered or combinatorial with an activehigh or active-low output. The output configuration is determined by two global bits and one local bit controlling four multiplexers in each macrocell.
 AMD’s FusionPLD program allows PALCE16V8 designs to be implemented using a wide variety of popular industry-standard design tools. By working closely with the FusionPLD partners, AMD certifies that the tools provide accurate, quality support. By ensuring that thirdparty tools are available, costs are lowered because a designer does not have to buy a complete set of new tools for each device. The FusionPLD program also greatly reduces design time since a designer can use a tool that is already installed and familiar.

DISTINCTIVE CHARACTERISTICS
* Pin and function compatible with all 20-pin GAL devices
* Electrically erasable CMOS technology provides reconfigurable logic and full testability
* High-speed CMOS technology
— 5-ns propagation delay for “-5” version
— 7.5-ns propagation delay for “-7” version
* Direct plug-in replacement for the PAL16R8 series and most of the PAL10H8 series
* Outputs programmable as registered or combinatorial in any combination
* Peripheral Component Interconnect (PCI) compliant
* Programmable output polarity
* Programmable enable/disable control
* Preloadable output registers for testability
* Automatic register reset on power up
* Cost-effective 20-pin plastic DIP, PLCC, and SOIC packages
* Extensive third-party software and programmer support through FusionPLD partners
* Fully tested for 100% programming and functional yields and high reliability
* 5 ns version utilizes a split leadframe for improved performance

PALCE16V8H-5 PALCE16V8H-7 PALCE16V8H-10 PALCE16V8Q-10 PALCE16V8H-15
PALCE16V8Q-15 PALCE16V8Q-20 PALCE16V8H-25 PALCE16V8Q-25

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GENERAL DESCRIPTION
The Am29LV800 is an 8 Mbit, 3.0 Volt-only Flash memory organized as 1 Mbyte of 8 bits each or 512K words of 16 bits each. For flexible erase and program capability, the 8 Mbits of data is divided into 19 sectors of one 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and fifteen 64 Kbytes. The x8 data appears on DQ0–DQ7; the x16 data appears on DQ0–DQ15. The Am29LV800 is offered in 44-pin SO and 48-pin TSOP packages. This device is designed to be programmed in-system with
the standard system 3.0 Volt V CC supply. The device can also be reprogrammed in standard EPROM programmers. The Am29LV800 provides two levels of performance. The first level offers access times as fast as 100 ns with a V CC range as low as 2.7 volts, which is optimal for
battery powered applications. The second level offers a 90 ns access time, optimizing performance in systems where the power supply is in the regulated range of 3.0 to 3.6 volts. To eliminate bus contention, the device has separate chip enable (CE), write enable (WE), and
output enable (OE) controls. The Am29LV800 is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Am29LV800T-100 Am29LV800B-100 Am29LV800T-120 Am29LV800B-120
TAG CMOS, Memory

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GENERAL DESCRIPTION
The MACH110 is a member of AMD’s high-performance EE CMOS MACH 1 family. This device has approximately three times the logic macrocell capability of the popular PAL22V10 without loss of speed. The MACH110 consists of two PAL blocks interconnected by a programmable switch matrix. The two PAL blocks are essentially “PAL22V16” structures complete with product-term arrays and programmable macrocells. The switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently. The MACH110 macrocell provides either registered or combinatorial outputs with programmable polarity. If a
registered configuration is chosen, the register can be configured as D-type or T-type to help reduce the number of product terms. The register type decision can be made by the designer or by the software. All macrocells can be connected to an I/O cell. If a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees up the I/O pin for use as an input.

DISTINCTIVE CHARACTERISTICS
- 44 Pins
- 32 Macrocells
- 12 ns tPD Commercial
  14 ns tPD Industrial
- 77 MHz fCNT
- 38 Inputs
- 32 Outputs
- 32 Flip-flops; 2 clock choices
- 2 “PAL22V16” Blocks
- Pin-compatible with MACH111, MACH210, MACH211, MACH215

MACH110-15 MACH110-20
TAG CMOS, Logic

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GENERAL DESCRIPTION
The Am29LV640DU/Am29LV641DU is a 64 Mbit, 3.0 Volt (3.0 V to 3.6 V) single power supply flash memory devices organized as 4,194,304 words. Data appears on DQ0-DQ15. The device is designed to be programmed in-system with the standard system 3.0 volt VCC supply. A 12.0 volt VPP is not required for program or erase operations. The device can also be programmed in standard EPROM programmers.
Access times of 90 and 120 ns are available for applications where VIO ≥ VCC. Access times of 100 and 120 ns are available for applications where VIO < VCC. The device is offered in 48-pin TSOP, 56-pin SSOP, 63-ball Fine-Pitch BGA and 64-ball Fortified BGA packages. To eliminate bus contention each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.
Each device requires only a single 3.0 Volt power supply (3.0 V to 3.6 V) for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.
The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations Reading data out of the device is similar to reading from other Flash or EPROM devices.
Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm-an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm-an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.

FEATURE
? Single power supply operation
? VersatileI control
? High performance
? Manufactured on 0.23 µm process technology
? CFI (Common Flash Interface) compliant
? SecSi (Secured Silicon) Sector region
? Ultra low power consumption (typical values at 3.0 V, 5 MHz)
? Flexible sector architecture
? Sector Protection
? Embedded Algorithms
? Compatibility with JEDEC standards
? Minimum 1 million erase cycle guarantee per sector
? Erase Suspend/Erase Resume
? Data# Polling and toggle bits
? Unlock Bypass Program command
? Ready/Busy# pin (RY/BY#) (Am29LV640DU in FBGA package only)
? Hardware reset pin (RESET#)
? WP# pin (Am29LV641DH/DL in TSOP, Am29LV640DH/DL in SSOP only)
? Program and Erase Performance (VHH not applied to the ACC input pin)

AM29LV640D, AM29LV641D, AM29LV640DH90R, AM29LV641DH90R, AM29LV640DL90R, AM29LV641DL90R, AM29LV640DU90R, AM29LV641DU90R, AM29LV640DH101R, AM29LV641DH101R, AM29LV640DL101R, AM29LV641DL101R, AM29LV640DU101R, AM29LV641DU101R, AM29LV640DH120R, AM29LV641DH120R, AM29LV640DL120R, AM29LV641DL120R, AM29LV640DU120R, AM29LV641DU120R, AM29LV640DH121R, AM29LV641DH121R, AM29LV640DL121R, AM29LV641DL121R, AM29LV640DU121R, AM29LV641DU121R

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GENERAL DESCRIPTION
The Am29DL322D/323D/324D family consists of 32 megabit, 3.0 volt-only flash memory devices, organized as 2,097,152 words of 16 bits each or 4,194,304 bytes of 8 bits each. Word mode data appears on DQ0–DQ15; byte mode data appears on DQ0–DQ7.
The device is designed to be programmed in-system with the standard 3.0 volt VCC supply, and can also be programmed in standard EPROM programmers.
The devices are available with an access time of 70, 90 or 120 ns. The devices are offered in 48-pin TSOP and 63-ball FBGA packages. Standard control pins—chip enable (CE#), write enable (WE#), and output enable (OE#)—control normal read and write operations, and avoid bus contention issues.
The devices requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.

HARDWARE FEATURES
■ Any combination of sectors can be erased
■ Ready/Busy# output (RY/BY#)
 - Hardware method for detecting program or erase cycle completion
■ Hardware reset pin (RESET#)
  - Hardware method of resetting the internal state machine to the read mode
■ WP#/ACC input pin
  - Write protect (WP#) function allows protection of two outermost boot sectors, regardless of sector protect status
  - Acceleration (ACC) function accelerates program timing
■ Sector protection
  - Hardware method of locking a sector, either in-system or using programming equipment, to
prevent any program or erase operation within that sector
  - Temporary Sector Unprotect allows changing data in protected sectors in-system

AM29DL322DT70, AM29DL323DT70, AM29DL324DT70, AM29DL322DB70, AM29DL323DB70, AM29DL324DB70, AM29DL322DT90, AM29DL323DT90, AM29DL324DT90, AM29DL322DB90, AM29DL323DB90, AM29DL324DB90, AM29DL322DT120, AM29DL323DT120, AM29DL324DT120, AM29DL322DB120, AM29DL323DB120, AM29DL324DB120
TAG CMOS, Memory

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