GENERAL DESCRIPTION
The Am79761 Gigabit Ethernet Physical Layer Serializer/Deserializer (GigaPHY-SD) device is a 1.25 Gbps Ethernet Transceiver optimized for Gigabit Ethernet/1000BASE-X applications. It implements the Physical Medium Attachment (PMA) layer for a single port.
The GigaPHY-SD device can interface to fiber-optic media to support 1000BASE-LX and 1000BASE-SX applications and can interface to copper coax to support 1000BASE-CX applications.
The functions performed by the device include serializing the 8B/10B 10-bit data for transmission, deserializing received code groups, recovering the clock from the incoming data stream, and word synchronization.
When transmitting, the GigaPHY-SD device receives 10-bit 8B/10B code groups at 125 million code groups per second. It then serializes the parallel data stream, adding a reference clock, and transmits it through the PECL drivers.
When receiving, the GigaPHY-SD device receives the PECL data stream from the network. It then recovers the clock from the data stream, deserializes the data stream into a 10-bit code group, and transmits it to the Physical Coding Sublayer (PCS) logic above. Optionally, it detects comma characters used to align the incoming word.

DISTINCTIVE CHARACTERISTICS
*Gigabit Ethernet Transceiver operates at 1.25 Gigabits per second (Gbps)
*Suitable for both Coaxial and Optical Link applications
*10-bit TTL Interface for Transmit and Receive Data
*Monolithic Clock Synthesis and Clock Recovery requires no external components
*Word Synchronization Function (Comma Detect)
*Low Power Operation - 700 mW typical
*64-pin Standard PQFP
-14 x 14 mm (0° C - 70° C)
-10 x 10 mm (0° C - 50° C)
*125 MHz TTL Reference Clock
*Loopback Diagnostic
*Single +3.3 V Supply

AM79761YC-10, AM79761YC-14

GENERAL DESCRIPTION
The Am27C040 is a 4 Mbit ultraviolet erasable programmable read-only memory. It is organized as 512K bytes, operates from a single +5 V supply, has a static standby mode, and features fast single address location programming. The device is available in windowed ceramic DIP packages and plastic one-time programmable (OTP) packages.
Data can be typically accessed in less than 90 ns, allowing high-performance microprocessors to operate without any WAIT states. The device offers separate Output Enable (OE#) and Chip Enable (CE#) controls, thus eliminating bus contention in a multiple bus microprocessor
system.
AMD’s CMOS process technology provides high speed, low power, and high noise immunity. Typical power consumption is only 100 mW in active mode, and 50 μW in standby mode.
All signals are TTL levels, including programming signals. Bit locations may be programmed singly, in blocks, or at random. The device supports AMD’s Flashrite programming algorithm (100 μs pulses) resulting in typical programming time of 1 minute.

DISTINCTIVE CHARACTERISTICS
*Fast access time
-Available in speed options as fast as 90 ns
*Low power consumption
-<10 μA typical CMOS standby current
*JEDEC-approved pinout
-Plug-in upgrade for 1 Mbit and 2 Mbit EPROMs
-Easy upgrade from 28-pin JEDEC EPROMs
*Single +5 V power supply
*±10% power supply tolerance standard
*100% Flashrite™ programming
-Typical programming time of 1 minute
*Latch-up protected to 100 mA from –1 V to VCC + 1 V
*High noise immunity
*Compact 32-pin DIP, PDIP, PLCC packages

AM29F400BT-45EC0, AM29F400BB-45EC0, AM29F400BT-45FC0

GENERAL DESCRIPTION
The PCnet-ISA+ controller, a single-chip Ethernet controller, is a highly integrated system solution for the,PC-AT Industry Standard Architecture (ISA ) architecture. It is designed to provide flexibility and compatibility with any existing PC application. This highly integrated
132-pin VLSI device is specifically designed to reduce parts count and cost, and addresses applications where higher system throughput is desired. The PCnet-ISA+ controller is fabricated with AMD’s advanced low-power CMOS process to provide low standby current for power sensitive applications.
The PCnet-ISA+ controller is a DMA-based device with a dual architecture that can be configured in two different operating modes to suit a particular PC application. In the Bus Master Mode all transfers are performed using the integrated DMA controller. This configuration enhances system performance by allowing the PCnet-ISA+ controller to bypass the platform DMA controller and directly address the full 24-bit memory space. The implementation of Bus Master Mode allows minimum parts count for the majority of PC applications. The PCnet-ISA+ controller can be configured to perform Shared Memory operations for compatibility with lowend
machines, such as PC/XTs that do not support Bus Master and high-end machines that require local packet buffering for increased system latency.
The PCnet-ISA+ controller is designed to directly interface with the ISA or EISA system bus. It contains an ISA Plug and Play bus interface unit, DMA Buffer Management Unit, 802.3 Media Access Control function, individual 136-byte transmit and 128-byte receive FIFOs, IEEE 802.3 defined Attachment Unit Interface (AUI), and a Twisted Pair Transceiver Media Attachment Unit. The PCnet-ISA+ controller is also register compatible with the LANCE (Am7990) Ethernet controller and PCnet-ISA. The DMA Buffer Management Unit supports the LANCE descriptor software model. External remote boot and Ethernet physical address PROMs and Electrically Erasable Proms are also supported.
This advanced Ethernet controller has the built-in capability of automatically selecting either the AUI port or the Twisted Pair transceiver. Only one interface is active at any one time. The individual 136-byte transmit and 128-byte receive FIFOs optimize system overhead, providing sufficient latency during packet transmission and reception, and minimizing intervention during normal network error recovery. The integrated Manchester encoder/decoder eliminates the need for an external Serial Interface Adapter (SIA) in the node system. If support for an external encoding/decoding scheme is desired, the embedded General Purpose Serial Interface (GPSI)
allows direct access to/from the MAC. In addition, the device provides programmable on-chip LED drivers for transmit, receive, collision, receive polarity, link integrity and activity, or jabber status. The PCnet-ISA+ controller also provides an External Address Detection Interfaceä (EADIä) to allow external hardware address filtering in internetworking applications.

Am79C98, Am79C100, Am7996, Am79C981, Am79C987, Am79C940, Am79C90, Am79C960, Am79C965, Am79C970

GENERAL DESCRIPTION
The Am29F016D is a 16 Mbit, 5.0 volt-only Flash memory organized as 2,097,152 bytes.
The 8 bits of data appear on DQ0–DQ7.
The Am29F016D is offered in 48-pin TSOP, 40-pin TSOP, and 44-pin SO packages.
The device is also available in Known Good Die (KGD) form.
For more information, refer to publication number 21551.
This device is designed to be programmed in-system with the standard system 5.0 volt VCC supply.
A 12.0 volt VPP is not required for program or erase operations.
The device can also be programmed in standard EPROM programmers.
This device is manufactured using AMD’s 0.23 μm process technology, and offers all the features and benefits of the Am29F016, which was manufactured using 0.5 μm process technology.
The standard device offers access times of 70, 90, 120, and 150 ns, allowing high-speed microprocessors to operate without wait states.
To eliminate bus contention, the device has separate chip enable (CE#), write enable (WE#), and output enable (OE#) controls.
The device requires only a single 5.0 volt power supply for both read and write functions.
Internally generated and regulated voltages are provided for the program and erase operations.
The device is entirely command set compatible with the JEDEC single-power-supply Flash standard.
Commandsare written to the command register using standard microprocessor write timings.
Register contents serve as input to an internal state-machine that controls the erase and programming circuitry.
Write cycles also internally latch addresses and data needed for the programming and erase operations.
Reading data out of the device is similar to reading from other Flash or EPROM devices.
Device programming occurs by executing the program command sequence.
This initiates the Embedded Program algorithm-an internal algorithm that automatically
times the program pulse widths and verifies proper cell margin.
Device erasure occurs by executing the erase command sequence.
This initiates the Embedded Erase algorithm-an internal algorithm that automatically
preprograms the array (if it is not already programmed) before executing the erase operation.
During erase, the device automatically times the erase pulse widths and verifies proper cell margin.
The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits.
After a program or erase cycle has been completed, the device is ready to read array data or accept another command.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors.
The device is fully erased when shipped from the factory.
Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions.
The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory.
This can be achieved via programming equipment.
The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure.
True background erase can thus be achieved.
The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data.
The RESET# pin may be tied to the system reset circuitry.
A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.
The system can place the device into the standby mode.
Power consumption is greatly reduced in this mode.
AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness.
The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.

DISTINCTIVE CHARACTERISTICS
*5.0 V ± 10%, single power supply operation
 -Minimizes system level power requirements
*Manufactured o 0.23 μm process technology
 -Compatible with 0.5 μm Am29F016 and 0.32 μm Am29F016B devices
*High performance
 -Access times as fast as 70 ns
*Low power consumption
 -25 mA typical active read current
 -30 mA typical program/erase current
 -1 μA typical standby current (standard access time to active mode)
*Flexible sector architecture
-32 uniform sectors of 64 Kbytes each
-Any combinatio of sectors ca be erased
-Supports full chip erase
-Group sector protection:
A hardware method of locking sector groups to prevent any program or erase operations within
that sector group
Temporary Sector Group Unprotect allows code changes i previously locked sectors
*Embedded Algorithms
-Embedded Erase algorithm automatically preprograms and erases the entire chip or any  combinatio of designated sectors
-Embedded Program algorithm automatically writes and verifies bytes at specified addresses
*Unlock Bypass Program Command
-Reduces overall programming time whe issuing multiple program command sequences
*Minimum 1,000,000 program/erase cycles per sector guaranteed
*20-year data retentio at 125°C
-Reliable operatio for the life of the system
*Package options
-48-pi and 40-pi TSOP
-44-pi SO
-Know Good Die (KGD) (see publicatio number 21551)
*Compatible with JEDEC standards
-Pinout and software compatible with single-power-supply Flash standard
-Superior inadvertent write protection
*Data# Polling and toggle bits
-Provides a software method of detecting program or erase cycle completion
*Ready/Busy# output (RY/BY#)
-Provides a hardware method for detecting program or erase cycle completion
*Erase Suspend/Erase Resume
-Suspends a sector erase operatio to read data from, or program data to, a non-erasing sector,
the resumes the erase operation
*Hardware reset pi(RESET#)
-Resets internal state machine to the read mode

Am29F016D-70FI
Am29F016D-70E4C
Am29F016D-70F4E

GENERAL DESCRIPTION
 The Am27C040 is a 4 Mbit ultraviolet erasable programmable read-only memory.
It is organized as 512K bytes, operates from a single +5 V supply, has a static standby mode, and features fast single address location programming.
The device is available in windowed ceramic DIP packages and plastic one-time programmable
(OTP) packages.
Data can be typically accessed in less than 90 ns, allowing high-performance microprocessors to operate without any WAIT states.
The device offers separate Output Enable (OE#) and Chip Enable (CE#) controls, thus eliminating bus contention in a multiple bus microprocessor system.
AMD’s CMOS process technology provides high speed, low power, and high noise immunity. Typical power consumption is only 100 mW in active mode, and 50 μW in standby mode.
All signals are TTL levels, including programming signals.
Bit locations may be programmed singly, in blocks, or at random.
The device supports AMD’s Flashrite programming algorithm (100 μs pulses) resulting in typical programming time of 1 minute.

DISTINCTIVE CHARACTERISTICS
* Fast access time
- Available in speed options as fast as 90 ns
* Low power consumption
- <10 μA typical CMOS standby current
* JEDEC-approved pinout
- Plug-in upgrade for 1 Mbit and 2 Mbit EPROMs
- Easy upgrade from 28-pin JEDEC EPROMs
* Single +5 V power supply
* ±10% power supply tolerance standard
* 100% Flashrite™ programming
- Typical programming time of 1 minute
* Latch-up protected to 100 mA from –1 V to VCC + 1 V
* High noise immunity
* Compact 32-pin DIP, PDIP, PLCC packages

AM27C040-90
AM27C040-120
AM27C040-150
AM27C040-200

DISTINCTIVE CHARACTERISTICS
* High-Performance Design
-66-MHz operating frequency
-Frequent instructions execute in one clock
-105.6-million bytes/second burst bus at 33 MHz
-Flexible write-through address control
-Dynamic bus sizing for 8-, 16-, and 32-bit buses
-Soft reset capability
* High On-Chip Integration
-8-Kbyte unified code and data cache
-Floating-point unit
-Paged, virtual memory management
* Enhanced System and Power Management
-Stop clock control for reduced power consumption
-Industry-standard, two-pin System Management Interrupt (SMI) for power management independent of processor operating mode and operating system
-Static design with Auto Halt Power-Down support
-Wide range of chipsets supporting SMM available to allow product differentiation
* Complete 32-Bit Architecture
-Address and data buses
-All registers
-8-, 16-, and 32-bit data types
* Standard Features
-3-V core with 5-V-tolerant I/O
-Binary compatible with all Am486® DX and Am486DX2 microprocessors
-Wide range of support available through the AMDâ FusionE86SM Program
* IEEE 1149.1 JTAG Boundary-Scan Compatibility
* Supports Environmental Protection Agency's Energy Star program
-3-V operation reduces power consumption up to 40%
-Energy management capability provides an excellent base for energy-efficient design
-Works with a variety of energy-efficient, powermanaged devices
* 208-Lead SQFP or 168-Pin PGA Package

GENERAL DESCRIPTION
The Am486DE2 microprocessor is an addition to the AMD Am486 microprocessor family. The Am486DE2 enhances system performance by incorporating flexible clock control and enhanced SMM.
The Am486DE2 CPU clock control feature permits the CPU to be stopped under controlled conditions, allowing reduced power consumption during system inactivity.
The SMM function is implemented with an industry-standard, two-pin interface.

AM486DE2-66V8THC
AM486DE2-66V8TGC

DISTINCTIVE CHARACTERISTICS
* Member of the E86™ CPU series
– 16-bit data bus
– 24-bit address bus
– 16-Mbyte address range
– Long-term stable supply from AMD
* 40-, 33- and 25-MHz operating speeds
* Ideal for embedded applications
– True Static design for low-power applications
– 3–5 V operation (at 25 MHz)
– Ideal for cost-sensitive designs
– True DC (0 MHz) operation
* Industry Standard Architecture
– Supports world’s largest software base for x86 architectures
– Wide range of chipsets and BIOS available
– Fully compatible with all 386SX systems and software
* System Management Mode (SMM) for system and power management (Am386SXLV only)
– System Management Interrupt (SMI) for power management independent of processor operating mode and operating system
– SMI coupled with I/O instruction break feature provides transparent power off and auto resume of peripherals which may not be “power aware”
– SMI is non-maskable and has higher priority than Non-Maskable Interrupt (NMI)
– Automatic save and restore of the microprocessor state
* 100-lead Plastic Quad Flat Pack (PQFP) package
* Extended temperature version available

GENERAL DESCRIPTION
The Am386®SX/SXL/SXLV microprocessors are lowcost, high-performance CPUs for embedded applications.
Embedded customers benefit from using the Am386 microprocessor in a number of ways.
The Am386SX/SXL/SXLV microprocessors provide embedded customers access to very inexpensive processors and the highest performance of any 386SX available anywhere. The 16-bit data path allows for inexpensive memory design. Full static operation, coupled with 3-V supplies, benefit customers who desire low-power designs. Standby Mode allows the Am386SXL/SXLV microprocessors to be clocked down to 0 MHz (DC) and retain full register contents. A float pin places all outputs in a three-state mode to facilitate board test and debug. Additionally, the Am386SXLV microprocessor comes with System Management Mode (SMM) for system and power management. SMI (System Management Interrupt) is a non-maskable, higher priority interrupt than NMI and has its own code space (1 Mbyte in Real Mode and 16 Mbyte in Protected Mode). SMI can be coupled with the I/O instruction break feature to implement transparent power management of peripherals.
SMM can be used by system designers to implement system and power management code independent of the operating system or the processor mode. Since the Am386SX/SXL/SXLV microprocessors are supported as an embedded product in the E86 family, customers can rely on long-term supply of product, and extended temperature products.
In addition, customers have access to the largest selection of inexpensive development tools, compilers, and chipsets. A large number of PC operating systems and Real Time Operating Systems (RTOS) support the Am386SX/SXL/SXLV microprocessors. This means cheaper development costs, and improved time to market.
The Am386SX/SXL/SXLV microprocessor is available in a small footprint 100-pin Plastic Quad Flat Pack (PQFP) package.

NG80386SX-33
NG80386SX-40

DISTINCTIVE CHARACTERISTICS
*Integrated Controller with Manchester encoder/decoder and 10BASE-T transceiver and AUI port
*Supports IEEE 802.3/ANSI 8802-3 and Ethernet standards
*84-pin PLCC and 100-pin PQFP Packages
*80-pin Thin Quad Flat Pack (TQFP) package available for space critical applications such as
PCMCIA
*Modular architecture allows easy tuning to specific applications
*High speed, 16-bit synchronous host system interface with 2 or 3 cycles/transfer
*Individual transmit (136 byte) and receive (128 byte) FlFOs provide increase of system latency
and support the following features:
— Automatic retransmission with no FIFO reload
— Automatic receive stripping and transmit padding (individually programmable)
— Automatic runt packet rejection
— Automatic deletion of collision frames
— Automatic retransmission with no FIFO reload
*Direct slave access to all on board configuration/status registers and transmit/ receive FlFOs
*Direct FIFO read/write access for simple interface to DMA controllers or l/O processors
*Arbitrary byte alignment and little/big endian memory interface supported
*Internal/external loopback capabilities
*External Address Detection Interface (EADI) for external hardware address filtering in
bridge/router applications
*JTAG Boundary Scan (IEEE 1149.1) test access port interface for board level production test
*Integrated Manchester Encoder/Decoder
*Digital Attachment Interface (DAI) allows by-passing of differential Attachment Unit Interface (AUI)
*Supports the following types of network

interface:
— AUI to external 10BASE2, 10BASE5 or 10BASE-F MAU
— DAI port to external 10BASE2, 10BASE5, 10BASE-T, 10BASE-F MAU
— General Purpose Serial Interface (GPSI) to external encoding/decoding scheme
— Internal 10BASE-T transceiver with automatic selection of 10BASE-T or AUI port
*Sleep mode allows reduced power consumption for critical battery powered applications
*5 MHz-25 MHz system clock speed
*Support for operation in industrial temperature range (–40°C to +85°C) available in all three
packages

GENERAL DESCRIPTION
The Media Access Controller for Ethernet (MACE) chip is a CMOS VLSI device designed to provide flexibility in customized LAN design. The MACE device is specifically designed to address applications where multiple I/O peripherals are present, and a centralized or system
specific DMA is required. The high speed, 16-bit synchronous system interface is optimized for an external DMA or I/O processor system, and is similar to many existing peripheral devices, such as SCSI and serial link controllers.
The MACE device is a slave register based peripheral. All transfers to and from the system are performed using simple memory or I/O read and write commands. In conjunction with a user defined DMA engine, the MACE chip provides an IEEE 802.3 interface tailored to a specific application. Its superior modular architecture and versatile system interface allow the MACE
device to be configured as a stand-alone device or as a connectivity cell incorporated into a larger, integrated system.


AM79C940
AM79C940

Features
 The AMD-760MPX™ and AMD-760MP™ chipsets are highly integrated system logic solutions that deliver enhanced performance for the AMD Athlon™ processor and other AMD Athlon processor system bus-compatible processors. The AMD-760MPX chipset consists of the AMD-762™ system controller in a 949-pin Ceramic Column Grid Array (CCGA) package and the AMD-768™ peripheral bus controller. The AMD-760MP chipset consists of the AMD-762 system controller in a CCGA package and the AMD-766™ peripheral bus controller.
 
 The AMD-762 system controller features the AMD Athlon system bus, system memory controller, Accelerated Graphics Port (AGP) controller, and Peripheral Component Interconnect PCI) bus controller. Figure 1 on page 5 shows a block diagram for the AMD-760MPX chipset. Figure 2 on page 6 shows a block diagram for the AMD-760MP chipset.
The AMD-762 system controller is designed with the following features:

* Two AMD Athlon processor system buses support the high-speed, split-transaction AMDAthlon system bus interface. These buses are designed to operate at 100/200-MHz or 133/266-MHz double-data rate.
* A 66/33-MHz 64/32-bit PCI 2.2-compliant bus interface supports up to seven bus masters plus the AMD-766 peripheral bus controller at 33 MHz or up to two bus masters plus the AMD-768 peripheral bus controller at 66 MHz.
* The 66-MHz AGP 2.0-compliant interface supports 1x, 2x, and 4x data transfer mode.
* High-speed memory—The AMD-762 system controller is designed to support DDR SDRAM DIMMs, operating at either 100/200-MHz or 133/266-MHz double-data rate. Note that the DDR interface speed is always locked to the frontside bus speed. This document describes the features and operation of the AMD-762 system controller. For a description of the AMD-766
peripheral bus controller, see the AMD-766™ Peripheral Bus Controller Data Sheet, order# 23167. For a description of the AMD-768 peripheral bus controller, see the AMD-768™ Peripheral Bus Controller Data Sheet, order# 24467. Key features of the AMD-762 system controller are provided in this section.

AMD Athlon™ System Buses
The AMD Athlon system buses have the following features:
* High-performance point-to-point system bus topology
* Source-synchronous clocking for high-speed transfers
* 200- or 266-MHz, split-transaction AMD Athlon system bus interface
* 1.6 Gbytes/s peak data transfer rates at 100/200 MHz, 2.1 Gbytes at 133/266 MHz Large 64-byte (cache line) data burst transfers

Integrated Memory Controller
The integrated memory controller has the following features:
* The AMD-762 system controller supports the following concurrencies:
* Processor-to-main-memory with PCI-to-main-memory
* Processor-to-main-memory with AGP-to-main-memory
• Processor-to-PCI with PCI-to-main-memory or AGP-to-main-memory
* Memory Error Correcting Code (ECC) support
* Supports the following DRAM:
• Supports 64-Mbit, 128-Mbit, 256-Mbit, and 512-Mbit technology
• 64-bit data width, plus 8-bit ECC paths
• Flexible row and column addressing
* Supports up to 4 Gbytes of memory
  Four open pages within one CS (device selected by chip select)

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES
■ Single power supply operation
— 3 volt read, erase, and program operations
■ VersatileI/OTM control
— Device generates data output voltages and tolerates data input voltages on the CE# and DQ inputs/outputs as determined by the voltage on the VIO pin; operates from 1.65 to 3.6 V
■ Manufactured on 0.23 µm MirrorBitTM process technology
■ SecSi™ (Secured Silicon) Sector region
— 128-doubleword/256-word sector for permanent, secure identification through an 8 doubleword/16-word random Electronic Serial Number, accessible through a command sequence
— May be programmed and locked at the factory or by the customer
■ Flexible sector architecture
— One hundred twenty-eight 32 Kdoubleword (64 Kword) sectors
■ Compatibility with JEDEC standards
— Provides pinout and software compatibility for single-power supply flash, and superior inadvertent write protection
■ 100,000 erase cycles per sector
■ 20-year data retention at 125°C
PERFORMANCE CHARACTERISTICS
■ High performance
— 100 ns access time
— 30 ns page read times
— 0.5 s typical sector erase time
— 22 µs typical write buffer doubleword programming time: 16-doubleword/32-word write buffer reduces overall programming time for multiple-word updates
— 4-doubleword/8-word page read buffer
— 16-doubleword/32-word write buffer
■ Low power consumption (typical values at 3.0 V, 5 MHz)
— 26 mA typical active read current
— 100 mA typical erase/program current
— 2 µA typical standby mode current
■ Package options
— 80-ball Fortified BGA
SOFTWARE & HARDWARE FEATURES
■ Software features
— Program Suspend & Resume: read other sectors before programming operation is completed
— Erase Suspend & Resume: read/program other sectors before an erase operation is completed
— Data# polling & toggle bits provide status
— Unlock Bypass Program command reduces overall multiple-word or byte programming time
— CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices
■ Hardware features
— Sector Group Protection: hardware-level method of preventing write operations within a sector group
— Temporary Sector Unprotect: VID-level method of changing code in locked sectors
— WP#/ACC input accelerates programming time
(when high voltage is applied) for greater throughput during system production. Protects first or last sector regardless of sector protection settings
— Hardware reset input (RESET#) resets device
— Ready/Busy# output (RY/BY#) detects program or erase cycle completion


GENERAL DESCRIPTION
 The Am29LV6402M consists of two 64 Mbit, 3.0 volt single power supply flash memory devices and is organized as 4,194,304 doublewords or 8,388,608 words. The device has a 32-bit wide data bus that can also function as an 16-bit wide data bus by using the WORD# input. The device can be programmed either in the host system or in standard EPROM programmers.

 An access time of 100 or 110 ns is available. Note that each access time has a specific operating voltage range (VCC) as specified in the Product Selector Guide and the Ordering Information sections. The device offered in an 80-ball Fortified BGA package. Each device
has separate chip enable (CE#), write enable WE#) and output enable (OE#) controls.
Each device requires only a single 3.0 volt power supply for both read and write functions. In addition VCC input, a high-voltage accelerated program WP#/ACC) input provides shorter programming times through increased current. This feature is intended facilitate factory throughput during system production, but may also be used in the field if desired.

 The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the device using standard microprocessor write timing. Write cycles also internally latch addresses and data needed for the programming and erase operations.

 The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Device programming and erasure are initiated through command sequences. Once a program or erase operation has begun, the host system need only poll the DQ7 and DQ15 (Data# Polling) or DQ6 and DQ14 oggle) status bits or monitor the Ready/Busy# RY/BY#) outputs to determine whether the operation is complete. To facilitate programming, an Unlock Bypass mode reduces command sequence overhead requiring only two write cycles to program data instead of four.

 The VersatileI/O™ (VIO) control allows the host system to set the voltage levels that the device generates and tolerates on the CE# control input and DQ I/Os the same voltage level that is asserted on the VIO pin. Refer to the Ordering Information section for valid VIO options.
Hardware data protection measures include a low

 VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming
equipment.

 The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. The Program Suspend/ Program Resume feature enables the host system
to pause a program operation in a given sector to read any other sector and then complete the program operation.