The PI3V341 is a true bi-directional 3-Port 4:1 multiplexer/demultiplexer with Hi-Z outputs that is recommended for both RGB and composite video switching applications. With the increased 4:1 channels, multiple components, such as VCR, DVD, PC1, PC2 and etc. can be put on the video networks. The VideoSwitch can be driven from a current output RAMDAC or voltage output composite video source.
Low On-Resistance, Low Crosstalk, Low OFF Isolation and wide bandwidth features make it ideal for video and other applications. Industry leading advantages include a near zero propagation delay, resulting from its low channel resistance and I/O capacitance. The switch is bi-directional and offers little or no attenuation of the high-speed signals at the outputs. The device also has exceptional high current capability which is far greater than most analog switches offered today. The PI3V341 offers a high-performance (375 MHz), low-cost solution to switch between video sources.
The PI3V341/-A is an enhanced solution w/ enhanced ESD protection support, up to 8kV contact.

*Near-Zero propagation delay
*5Ω switches connect inputs to outputs
*High signal passing bandwidth (375MHz)
*Beyond Rail-to-Rail switching
*5V I/O tolerant with 3.3V supply
*2.5V and 3.3V supply voltage operation
*Hot insertion capable (non '-A' part only)
*Low Crosstalk (XTALK = -60dB Typ.)
*Low Off-Isolation (OIRR = -60db Typ.)
*Industrial operating temperature: -40ºC to +85ºC
*ESD Protection
-PI3V341: I/O pins only have 3kV contact protection
-PI3V341-A: I/O pins only have 8kV contact protection
*Latch-up performance >250mA per JESD17
*Packaging (Pb-free & greeen available)
-24-Pin QSOP (Q)
-24-Pin TSSOP (L)

*Projection TV and LCD TV
*Video consumer applications
*Analog video signal processing

PI3V341QE, PI3V341LE, PI3V341-AQE, PI3V341-ALE

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Product Description
TQM640002 RF front end module (FEM) is an active device for GPS applications (center frequency 1575.42 MHz). It is designed for simultaneous GPS + voice in multi-function handsets. The FEM is comprised of a low-power flip-chip LNA die, a pair of high-performance SAW filters, and integrated passive matching circuitry. The module will operate at 1.8v or 2.8v bias and its current consumption – typically 5.0 mA – is not changed by DC supply, making it suitable for use in lowpower applications & during low-battery situations. The FEM performance exhibits high in-band gain and excellent rejection in all the key cellular & WLAN/Bluetooth bands. The device also exhibits both a high intercept point & a low noise figure, which optimally addresses today’s most stringent GPS front end receiver requirements.

*Low noise figure & high associated gain for high IP3 receiver stages for 1575 MHz
*NF = 1.56 dB; Gain=16 dB @ 1.8V
*No external matching components required
*Low current consumption & low voltage operation
*High immunity against inband compression due to out-of-band interferers during simultaneous GPS + voice operation
*Input and output internally pre-matched to 50 W
*Low cost miniature package 3 x 3 x 1.0 mm
-suitable for low profile handset applications
*Power-up control for the LNA
*Designed to operate at 1.8V, with enhanced linearity performance at 2.8V

*1575.42 MHz, L1 band GPS applications
*Personal Navigation Devices
*Cellular Handsets: Simultaneous GPS + voice calls

TQM640002GEL, TQM640002TR

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The S2042 and S2043 transmitter and receiver pair are designed to perform high-speed serial data transmission over fiber optic or coaxial cable interfaces conforming to the requirements of the ANSI X3T11 Fibre Channel specification. The chipset is selectable to 1062, 531 or 266 Mbit/s data rates with associated 10- or 20-bit data word.
The chipset performs parallel-to-serial and serial-toparallel conversion and framing for block-encoded data. The S2042 on-chip PLL synthesizes the highspeed clock from a low-speed reference. The S2043 on-chip PLL synchronizes directly to incoming digital signals to receive the data stream. The transmitter and receiver each support differential PECL-compatible I/O for fiber optic component interfaces, to minimize crosstalk and maximize data integrity. Local loopback allows for system diagnostics. The TTL I/O section can operate from either a +3.3V or a +5V power supply. With a 3.3V power supply the chipset dissipates only 1W typically.
Figure 1 shows a typical network configuration incorporating the chipset. The chipset is compatible with AMCC’s S2036 Open Fiber Control (OFC) device.

*Functionally compliant with ANSI X3T11 Fibre Channel physical and transmission protocol standards
*S2042 transmitter incorporates phase-locked loop (PLL) providing clock synthesis from low-speed reference
*S2043 receiver PLL configured for clock and data recovery
*1062, 531 and 266 Mb/s operation
*10- or 20-bit parallel TTL compatible interface
*1 watt typical power dissipation for chipset
*+3.3/+5V power supply
*Low-jitter serial PECL compatible interface
*Lock detect
*Local loopback
*10mm x 10mm 52 PQFP package
*Fibre Channel framing performed by receiver
*Continuous downstream clocking from receiver
*TTL compatible outputs possible with +5V I/O power supply

High-speed data communications
*Switched networks
*Proprietary extended backplanes
*Mass storage devices/RAID drives

S2043, S2042B-10, S2043B-10

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The Micron® QDR™II (Quad Data Rate™) synchronous, pipelined burst SRAM employs high-speed, lowpower CMOS designs using an advanced 6T CMOS process.
The QDR architecture consists of two separate DDR (double data rate) ports to access the memory array. The read port has dedicated data outputs to support READ operations. The write port has dedicated data inputs to support WRITE operations. This architecture eliminates the need for high-speed bus turnaround. Access to each port is accomplished using a common address bus. Addresses for reads and writes are latched on rising edges of the K and K# input clocks, respectively. Each address location is associated with two words that burst sequentially into or out of the device.
GENERAL DESCRIPTION (continued) Since data can be transferred into and out of the device on every rising edge of both clocks (K and K#, C and C#), memory bandwidth is maximized while system design is simplified by eliminating bus turnarounds.
Depth expansion is accomplished with port selects for each port (read R#, write W#), which are received at K rising edge. Port selects permit independent port operation.
All synchronous inputs pass through registers controlled by the K or K# input clock rising edges. Active LOW byte writes (BWx#) permit byte or nibble write selection. Write data and byte writes are registered on the rising edges of both K and K#. The addressing within each burst of two is fixed and sequential, beginning with the lowest and ending with the highest address. All synchronous data outputs pass through output registers controlled by the rising edges of the output clocks (C and C# if provided, otherwise K and K#).
Four balls are used to implement JTAG test capabilities: test mode select (TMS), test data-in (TDI), test clock (TCK), and test data-out (TDO). JTAG circuitry is used to serially shift data to and from the SRAM. JTAG inputs use JEDEC-standard 1.8V I/O levels to shift data during this testing mode of operation.
The SRAM operates from a +1.8V power supply, and all inputs and outputs are HSTL-compatible. The device is ideally suited for applications that benefit from a high-speed, fully-utilized DDR data bus.

*DLL circuitry for accurate output data placement
*Separate independent read and write data ports with concurrent transactions
*100 percent bus utilization DDR READ and WRITE operation
*Fast clock to valid data times
*Full data coherency, providing most current data
*Two-tick burst counter for low DDR transaction size
*Double data rate operation on read and write ports
*Two input clocks (K and K#) for precise DDR timing at clock rising edges only
*Two output clocks (C and C#) for precise flight time and clock skew matching—clock and data delivered together to receiving device
*Single address bus
*Simple control logic for easy depth expansion
*Internally self-timed, registered writes
*+1.8V core and HSTL I/O
*Clock-stop capability
*15mm x 17mm, 1mm pitch, 11 x 15 grid FBGA package
*User-programmable impedance output
*JTAG boundary scan

MT54W4MH9B, MT54W2MH18B, MT54W1MH36B

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The new LT series device provides reliable, noncycling protection against overcharging and short circuits events for rechargeable battery cells where resettable protection is desired.

*RoHS compliant and lead-free
*Weldable nickel terminals
*Compact design saves board space
*Low resistance
*Provides overcurrent protection at 100°C trip temperature

*Rechargeable battery cell protection
-Mobile phones
-Laptop computers

15LT070, 24LT100, 24LT180, 24LT190, 24LT260, 24LT300, 24LT310, 24LT340

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These digital charge-transfer (“QT”) QMatrix™ ICs are designed to detect human touch on up 48 keys when used with a scanned, passive X-Y matrix. They will project touch keys through almost any dielectric, e.g. glass, plastic, stone, ceramic, and even wood, up to thicknesses of 5 cm or more. The touch areas are defined as simple 2-part interdigitated electrodes of conductive material, like copper or screened silver or carbon deposited on the rear of a control panel. Key sizes, shapes and placement are almost entirely arbitrary; sizes and shapes of keys can be mixed within a single panel of keys and can vary by a factor of 20:1 in surface area. The sensitivity of each key can be set individually via simple functions over the SPI or UART port, for example via Quantum’s QmBtn program, or from a host microcontroller. Key setups are stored in an onboard eeprom and do not need to be reloaded with each powerup.
These devices are designed specifically for appliances, electronic kiosks, security panels, portable instruments, machine tools, or similar products that are subject to environmental influences or even vandalism. It can permit the construction of 100% sealed, watertight control panels that are immune to humidity, temperature, dirt accumulation, or the physical deterioration of the panel surface from abrasion, chemicals, or abuse. To this end the device contains Quantum-pioneered adaptive auto self-calibration, drift compensation, and digital filtering algorithms that make the sensing function robust and survivable.
The parts can scan matrix touch keys over LCD panels or other displays when used with clear ITO electrodes arranged in a matrix. They do not require 'chip on glass' or other exotic fabrication techniques, thus allowing the OEM to source the matrix from multiple vendors. Materials such as such common PCB materials or flex circuits can be used.
External circuitry consists of a resonator and a few passive parts, all of which can fit into a 6.5 sq cm footprint (1 sq inch). Control and data transfer is via either an SPI or UART port.
These devices make use of an important new variant of charge-transfer sensing, transverse charge-transfer, in a matrix format that minimizes the number of required scan lines. Unlike older methods, it does not require one IC per key.

*Advanced second generation QMatrix™ controller
*Keys individually adjustable for sensitivity, response time, and many other critical parameters
*Panel thicknesses to 50mm through any dielectric
*32 and 48 key versions
*100% autocal for life - no in-field adjustments
*SPI Slave and UART interfaces
*Sleep mode with wake pin
*Adjacent key suppression feature
*Synchronous noise suppression pin
*Spread-spectrum modulation: high noise immunity
*Mix and match key sizes & shapes in one panel
*Low overhead communications protocol
*FMEA compliant design features
*Negligible external component count
*Extremely low cost per key
*44-pin Pb-free TQFP package

*Automotive panels
*Machine tools
*ATM machines
*Appliance controls
*Outdoor keypads
*Security keypanels
*Industrial keyboards

QT60486, QT60486-AS-G, QT60326-AS-G, QT60486-AG, QT60326-AG


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General Description
The RT9247 is a multi-phase buck DC/DC controller integrated with all control functions for GHz CPU VRM. The RT9247 controls 2 or 3 buck switching stages operating in interleaved phase set automatically. The multi-phase architecture provides high output current while maintaining low power dissipation on power devices and low stress on input and output capacitors. The high equivalent operating frequency also reduces the component dimension and the output voltage ripple in load transient.
RT9247 controls both voltage and current loops to achieve good regulation, response & power stage thermal balance. Precise current loop using RDS(ON) as sense component builds precise load line for strict VRM DC & transient specification and also ensures thermal balance of different power stages. The settings of current sense, droop tuning, VCORE initial offset and over current protection are independent to compensation circuit of voltage loop. The feature greatly facilitates the flexibility of CPU power supply design and tuning.
The DAC output of RT9247 supports VRD10 by 6-bit VID input, precise initial value & smooth VCORE transient at VID jump. The IC monitors the VCORE voltage for PGOOD and over-voltage protection. Soft-start, over-current protection and programmable under-voltage lockout are also provided to assure the safety of microprocessor and power system.

*Multi-Phase Power Conversion with Automatic Phase Selection
*VRD10 DAC Output with Active Droop Compensation for Fast Load Transient
*Smooth VCORE Transition at VID Jump
*Power Stage Thermal Balance by RDS(ON) Current Sense
*Hiccup Mode Over-Current Protection
*Programmable Switching Frequency (50kHz to 400kHz per Phase), Under-Voltage Lockout and Soft-Start
*High Ripple Frequency Times Channel Number
*RoHS Compliant and 100% Lead (Pb)-Free

*Intel® Processors Voltage Regulator: VRD10
*Low Output Voltage, High Current DC-DC Converters
*Voltage Regulator Modules

RT9247PC, RT9247GC

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The ZHT431 is a three terminal adjustable shunt regulator offering excellent temperature stability and output current handling capability up to 100mA. The device offers extended operating temperature range working from -55 to +125°C. The output voltage may be set to any chosen voltage between 2.5 and 20 volts by selection of two external divider resistors.
The devices can be used as a replacement for zener diodes in many applications requiring an improvement in zener performance.

*Surface mount SOT223 and SOT23 packages
*2% and 1% tolerance
*Maximum temperature coefficient 67 ppm/°C
*Temperature compensated for operation over the full temperature range
*Programmable output voltage
*50A to 100mA current sink capability
*Low output noise
*Wide temperature range -55 to +125°C

*Series and shunt regulator
*Voltage monitor
*Over voltage / under voltage protection
*Switch mode power supplies


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The PDSP16350 provides an integrated solution to the need for very accurate, digitised, sine and cosine waveforms. Both these waveforms are produced simultaneously, with 16 bit amplitude accuracy, and are synthesised using a 34 bit phase accumulator. The more significant bits of this provide 16 bits of phase accuracy for the sine and cosine look up tables.
With a 20 MHz system clock, waveforms up to 10 MHz can be produced, with 0.001 Hz resolution. If frequency modulation is required with no discontinuities, the phase increment value can be changed linearly on every clock cycle. Alternatively absolute phase jumps can be made to any phase value.
The provision of two output multipliers allows the sine and cosine waveforms to be amplitude modulated with a 16 bit value present on the input port. This option can also be used to generate the in-phase and quadrature components from an incoming signal. This I/Q split function is required by systems which employ complex signal processing.

*Direct Digital Synthesiser producing simultaneous sine and cosine values
*16 bit phase and amplitude accuracy, giving spur levels down to - 90 dB
*Synthesised outputs from DC to 10 MHz with accuracies better than 0.001 Hz
*Amplitude and Phase modulation modes
*84 pin PGA or 132 pin QFP

*Numerically controlled oscillator (NCO)
*Quadrature signal generator
*FM, PM, or AM signal modulator
*Sweep Oscillator
*High density signal constellation applications with simultaneous amplitude and phase modulation
*VHF reference for UHF generators
*Signal demodulator

PDSP16350/B0/AC, PDSP16350/B0/GC, PDSP16350/A0/AC, PDSP16350/A0/GC

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The WM8720 is a high performance stereo DAC designed for audio applications such as CD, DVD, home theatre systems, set top boxes and digital TV. The WM8720 supports data input word lengths from 16 to 24-bits and sampling rates up to 96kHz. The WM8720 consists of a serial interface port, digital interpolation filter, multi-bit sigma delta modulator and stereo DAC in a small 20-pin SSOP package. The WM8720 also includes a digitally controllable mute and attenuator function on each channel.
The WM8720 supports a variety of connection schemes for audio DAC control. The SPI-compatible serial control port provides access to a wide range of features including onchip mute, attenuation and phase reversal. A hardware controllable interface is also available.
The programmable data input port supports a variety of glueless interfaces to popular DSPs, audio decoders and S/PDIF and AES/EBU receivers.

- 102dB SNR (‘A’ weighted @48kHz),
- THD: -95dB @ 0dB FS
*5V or 3.3V supply operation
*Sampling frequency: 8kHz to 96kHz
*Input data word: 16 to 24-bit
*Hardware or SPI compatible serial port control modes
- Hardware mode: system clock, reset, mute, de-emphasis
- Serial control mode: mute, de-emphasis, digital attenuation (256 steps), zero mute, phase reversal, power down

*CD, DVD audio
*Home theatre systems
*Set top boxes
*Digital TV

WM8720EDS, WM8720EDS/R, WM8720SEDS, WM8720SEDS/R

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