Description
The PI3V341 is a true bi-directional 3-Port 4:1 multiplexer/demultiplexer with Hi-Z outputs that is recommended for both RGB and composite video switching applications. With the increased 4:1 channels, multiple components, such as VCR, DVD, PC1, PC2 and etc. can be put on the video networks. The VideoSwitch can be driven from a current output RAMDAC or voltage output composite video source.
Low On-Resistance, Low Crosstalk, Low OFF Isolation and wide bandwidth features make it ideal for video and other applications. Industry leading advantages include a near zero propagation delay, resulting from its low channel resistance and I/O capacitance. The switch is bi-directional and offers little or no attenuation of the high-speed signals at the outputs. The device also has exceptional high current capability which is far greater than most analog switches offered today. The PI3V341 offers a high-performance (375 MHz), low-cost solution to switch between video sources.
The PI3V341/-A is an enhanced solution w/ enhanced ESD protection support, up to 8kV contact.

Features
*Near-Zero propagation delay
*5Ω switches connect inputs to outputs
*High signal passing bandwidth (375MHz)
*Beyond Rail-to-Rail switching
*5V I/O tolerant with 3.3V supply
*2.5V and 3.3V supply voltage operation
*Hot insertion capable (non '-A' part only)
*Low Crosstalk (XTALK = -60dB Typ.)
*Low Off-Isolation (OIRR = -60db Typ.)
*Industrial operating temperature: -40ºC to +85ºC
*ESD Protection
-PI3V341: I/O pins only have 3kV contact protection
-PI3V341-A: I/O pins only have 8kV contact protection
*Latch-up performance >250mA per JESD17
*Packaging (Pb-free & greeen available)
-24-Pin QSOP (Q)
-24-Pin TSSOP (L)

Applications
*Projection TV and LCD TV
*Video consumer applications
*Analog video signal processing

PI3V341QE, PI3V341LE, PI3V341-AQE, PI3V341-ALE

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Product Description
TQM640002 RF front end module (FEM) is an active device for GPS applications (center frequency 1575.42 MHz). It is designed for simultaneous GPS + voice in multi-function handsets. The FEM is comprised of a low-power flip-chip LNA die, a pair of high-performance SAW filters, and integrated passive matching circuitry. The module will operate at 1.8v or 2.8v bias and its current consumption – typically 5.0 mA – is not changed by DC supply, making it suitable for use in lowpower applications & during low-battery situations. The FEM performance exhibits high in-band gain and excellent rejection in all the key cellular & WLAN/Bluetooth bands. The device also exhibits both a high intercept point & a low noise figure, which optimally addresses today’s most stringent GPS front end receiver requirements.

Features
*Low noise figure & high associated gain for high IP3 receiver stages for 1575 MHz
*NF = 1.56 dB; Gain=16 dB @ 1.8V
*No external matching components required
*Low current consumption & low voltage operation
*High immunity against inband compression due to out-of-band interferers during simultaneous GPS + voice operation
*Input and output internally pre-matched to 50 W
*Low cost miniature package 3 x 3 x 1.0 mm
-suitable for low profile handset applications
*Power-up control for the LNA
*Designed to operate at 1.8V, with enhanced linearity performance at 2.8V
*Halogen-free

Applications
*1575.42 MHz, L1 band GPS applications
*Personal Navigation Devices
*Cellular Handsets: Simultaneous GPS + voice calls

TQM640002GEL, TQM640002TR

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  1. Subject: Fortnite esp

    Tracked from Fortnite esp 2019/11/02 09:47  삭제

    DATASHEETBLOG

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GENERAL DESCRIPTION
The S2042 and S2043 transmitter and receiver pair are designed to perform high-speed serial data transmission over fiber optic or coaxial cable interfaces conforming to the requirements of the ANSI X3T11 Fibre Channel specification. The chipset is selectable to 1062, 531 or 266 Mbit/s data rates with associated 10- or 20-bit data word.
The chipset performs parallel-to-serial and serial-toparallel conversion and framing for block-encoded data. The S2042 on-chip PLL synthesizes the highspeed clock from a low-speed reference. The S2043 on-chip PLL synchronizes directly to incoming digital signals to receive the data stream. The transmitter and receiver each support differential PECL-compatible I/O for fiber optic component interfaces, to minimize crosstalk and maximize data integrity. Local loopback allows for system diagnostics. The TTL I/O section can operate from either a +3.3V or a +5V power supply. With a 3.3V power supply the chipset dissipates only 1W typically.
Figure 1 shows a typical network configuration incorporating the chipset. The chipset is compatible with AMCC’s S2036 Open Fiber Control (OFC) device.

FEATURES
*Functionally compliant with ANSI X3T11 Fibre Channel physical and transmission protocol standards
*S2042 transmitter incorporates phase-locked loop (PLL) providing clock synthesis from low-speed reference
*S2043 receiver PLL configured for clock and data recovery
*1062, 531 and 266 Mb/s operation
*10- or 20-bit parallel TTL compatible interface
*1 watt typical power dissipation for chipset
*+3.3/+5V power supply
*Low-jitter serial PECL compatible interface
*Lock detect
*Local loopback
*10mm x 10mm 52 PQFP package
*Fibre Channel framing performed by receiver
*Continuous downstream clocking from receiver
*TTL compatible outputs possible with +5V I/O power supply

APPLICATIONS
High-speed data communications
*Supercomputer/Mainframe
*Workstation
*Switched networks
*Proprietary extended backplanes
*Mass storage devices/RAID drives

S2043, S2042B-10, S2043B-10

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