The Micron® QDR™II (Quad Data Rate™) synchronous, pipelined burst SRAM employs high-speed, lowpower CMOS designs using an advanced 6T CMOS process.
The QDR architecture consists of two separate DDR (double data rate) ports to access the memory array. The read port has dedicated data outputs to support READ operations. The write port has dedicated data inputs to support WRITE operations. This architecture eliminates the need for high-speed bus turnaround. Access to each port is accomplished using a common address bus. Addresses for reads and writes are latched on rising edges of the K and K# input clocks, respectively. Each address location is associated with two words that burst sequentially into or out of the device.
GENERAL DESCRIPTION (continued) Since data can be transferred into and out of the device on every rising edge of both clocks (K and K#, C and C#), memory bandwidth is maximized while system design is simplified by eliminating bus turnarounds.
Depth expansion is accomplished with port selects for each port (read R#, write W#), which are received at K rising edge. Port selects permit independent port operation.
All synchronous inputs pass through registers controlled by the K or K# input clock rising edges. Active LOW byte writes (BWx#) permit byte or nibble write selection. Write data and byte writes are registered on the rising edges of both K and K#. The addressing within each burst of two is fixed and sequential, beginning with the lowest and ending with the highest address. All synchronous data outputs pass through output registers controlled by the rising edges of the output clocks (C and C# if provided, otherwise K and K#).
Four balls are used to implement JTAG test capabilities: test mode select (TMS), test data-in (TDI), test clock (TCK), and test data-out (TDO). JTAG circuitry is used to serially shift data to and from the SRAM. JTAG inputs use JEDEC-standard 1.8V I/O levels to shift data during this testing mode of operation.
The SRAM operates from a +1.8V power supply, and all inputs and outputs are HSTL-compatible. The device is ideally suited for applications that benefit from a high-speed, fully-utilized DDR data bus.

*DLL circuitry for accurate output data placement
*Separate independent read and write data ports with concurrent transactions
*100 percent bus utilization DDR READ and WRITE operation
*Fast clock to valid data times
*Full data coherency, providing most current data
*Two-tick burst counter for low DDR transaction size
*Double data rate operation on read and write ports
*Two input clocks (K and K#) for precise DDR timing at clock rising edges only
*Two output clocks (C and C#) for precise flight time and clock skew matching—clock and data delivered together to receiving device
*Single address bus
*Simple control logic for easy depth expansion
*Internally self-timed, registered writes
*+1.8V core and HSTL I/O
*Clock-stop capability
*15mm x 17mm, 1mm pitch, 11 x 15 grid FBGA package
*User-programmable impedance output
*JTAG boundary scan

MT54W4MH9B, MT54W2MH18B, MT54W1MH36B

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The new LT series device provides reliable, noncycling protection against overcharging and short circuits events for rechargeable battery cells where resettable protection is desired.

*RoHS compliant and lead-free
*Weldable nickel terminals
*Compact design saves board space
*Low resistance
*Provides overcurrent protection at 100°C trip temperature

*Rechargeable battery cell protection
-Mobile phones
-Laptop computers

15LT070, 24LT100, 24LT180, 24LT190, 24LT260, 24LT300, 24LT310, 24LT340

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These digital charge-transfer (“QT”) QMatrix™ ICs are designed to detect human touch on up 48 keys when used with a scanned, passive X-Y matrix. They will project touch keys through almost any dielectric, e.g. glass, plastic, stone, ceramic, and even wood, up to thicknesses of 5 cm or more. The touch areas are defined as simple 2-part interdigitated electrodes of conductive material, like copper or screened silver or carbon deposited on the rear of a control panel. Key sizes, shapes and placement are almost entirely arbitrary; sizes and shapes of keys can be mixed within a single panel of keys and can vary by a factor of 20:1 in surface area. The sensitivity of each key can be set individually via simple functions over the SPI or UART port, for example via Quantum’s QmBtn program, or from a host microcontroller. Key setups are stored in an onboard eeprom and do not need to be reloaded with each powerup.
These devices are designed specifically for appliances, electronic kiosks, security panels, portable instruments, machine tools, or similar products that are subject to environmental influences or even vandalism. It can permit the construction of 100% sealed, watertight control panels that are immune to humidity, temperature, dirt accumulation, or the physical deterioration of the panel surface from abrasion, chemicals, or abuse. To this end the device contains Quantum-pioneered adaptive auto self-calibration, drift compensation, and digital filtering algorithms that make the sensing function robust and survivable.
The parts can scan matrix touch keys over LCD panels or other displays when used with clear ITO electrodes arranged in a matrix. They do not require 'chip on glass' or other exotic fabrication techniques, thus allowing the OEM to source the matrix from multiple vendors. Materials such as such common PCB materials or flex circuits can be used.
External circuitry consists of a resonator and a few passive parts, all of which can fit into a 6.5 sq cm footprint (1 sq inch). Control and data transfer is via either an SPI or UART port.
These devices make use of an important new variant of charge-transfer sensing, transverse charge-transfer, in a matrix format that minimizes the number of required scan lines. Unlike older methods, it does not require one IC per key.

*Advanced second generation QMatrix™ controller
*Keys individually adjustable for sensitivity, response time, and many other critical parameters
*Panel thicknesses to 50mm through any dielectric
*32 and 48 key versions
*100% autocal for life - no in-field adjustments
*SPI Slave and UART interfaces
*Sleep mode with wake pin
*Adjacent key suppression feature
*Synchronous noise suppression pin
*Spread-spectrum modulation: high noise immunity
*Mix and match key sizes & shapes in one panel
*Low overhead communications protocol
*FMEA compliant design features
*Negligible external component count
*Extremely low cost per key
*44-pin Pb-free TQFP package

*Automotive panels
*Machine tools
*ATM machines
*Appliance controls
*Outdoor keypads
*Security keypanels
*Industrial keyboards

QT60486, QT60486-AS-G, QT60326-AS-G, QT60486-AG, QT60326-AG


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