The MT90502 Multi-Channel AAL2 SAR bridges a standard TDM (Time Division Multiplexed) backplane to a standard ATM (Asynchronous Transfer Mode) bus.
The device provides the CPS (Common Part Sublayer) and SAR (Segmentation and Reassembly) engines.
The MT90502 has the capability of simultaneously processing 1023 bi-directional CIDs (AAL2 Channel Identifiers) and 1023 bi-directional VCs (Virtual Circuits).
The device can be connected directly to an H.110 compatible bus.
The TDM bus consists of 32 bi-directional serial data streams operating at 2.048, 4.096, or 8.192 Mbits/s.
The MT90502 directly accepts G.711 PCM (Pulse Code Modulation) and G.726 ADPCM (Adaptive Differential Pulse Code Modulation) traffic for packetisation.
For these two data formats, the device also implements silence suppression and comfort noise generation.
To support other voice compression algorithms, the MT90502 connects directly to commercially available DSPs through synchronous serial data streams.
The Variable Bit Rate (VBR) traffic is HDLC encapsulated and carried over the serial data streams.
The interface to the ATM domain is provided by three UTOPIA Level 1 ports (Ports A, B, and C). All three of the UTOPIA ports can operate in ATM (master) or PHY (slave) mode. Ports A and B combined, architects a compliant UTOPIA Level 2 Multi-PHY port.
The MT90502 provides the capability of routing ATM cells to different UTOPIA interfaces, SAR engine or CPU.
This feature can be used to connect another MT90502 (to support up to 2046 CID channels or 2046 phone calls) and/or to connect an external AAL1 and/or AAL5 SAR.

* AAL2 Segmentation Reassembly device capable of simultaneously processing up to 1023 active CIDs (AAL2 Channel Identifier) and 1023 active VCs (Virtual Circuits).
* Support for up to 255 CIDs per VC. Maximum of 1023 CIDs.
* Implements AAL2 Common Part Sub-layer (CPS) functions specified in ITU I.363.2.
* Implements AAL2 Service Specific Convergence Sub-layer (SSCS) functions for G.711 PCM and G.726 ADPCM voice.
* Supports 44-byte PCM or ADPCM packet profiles specified in AF-VMOA-0145.00.
* CPS packet payload can support up to 64-bytes.
* Supports over-subscription of 10:1.
* H.100/H.110 compatible TDM bus for PCM or ADPCM data. Supports both master and slave TDM bus clock operation.
* TDM bus also supports compressed voice such as ITU G.723, G.728 and G.729 through HDLC encapsulation.
* Three UTOPIA Level 1 ports configurable as PHY or ATM allowing for connection to an external AAL5 SAR processor, or for chaining multiple MT90502 devices. Ports A & B are configurable as a single 8-bit UTOPIA Level 2 PHY port with 5 ADDR lines.
* UTOPIA module provides a cell switching function with a header translation.
* Performs silence suppression for PCM and ADPCM.
* Comfort noise generation.
* Capability to inject and recover CPS packets through the CPU host processor bus.
* 8-bit or 16-bit microprocessor port, configurable to Motorola or Intel timing.
* Single rail 3.3 V, 456 PBGA.
* IEEE 1149 (JTAG) interface.

* Gateway
* ATM Edge Switch
* Next Generation Digital Loop Carrier
* Multiservice Switching Platform
* 3rd Generation Mobile System Equipment



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