The MPMB62D-68KX3 is 32M bit x 64 Double Data Rate Synchronous Dynamic RAM high density memory module based on 128Mb DDR SDRAM respectively.
The MPMB62D-68KX3 consists of sixteen CMOS 16M ´ 8 bit with 4 banks Double Data Rate Synchronous DRAMs in TinyBGA package and a 2K EEPROM in 8-Pin TSSOP package mounted on a 184pin glass-epoxy substrate.
Two 0.1μF decoupling capacitors are mounted on the printed circuit board in parallel for each DDR SDRAM.
The MPMB62D-68KX3 is a Dual In-line Memory Module and is intended for mounting into 184pin edge connector sockets.
Synchronous design allows precise cycle control with the use of system clock.
Data I/O transactions are possible on both edges of every clock cycle.
Range of operating frequencies, programmable latencies and burst lengths allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.

* Performance range - 166MHz ( DDR333, CL2.5 )
* Double-data-rate architecture; two data transfers per clock cycle
* Bi-directional data strobe (DQS)
* Differential clock inputs (CK and /CK)
* DLL aligns DQ and DQS transition with CK transition
* Auto & self refresh capability (4096 Cycles / 64ms)
* Single 2.5V ±0.2V power supply
* Programmable Read latency 2, 2.5 (clock)
* Programmable Burst length (2, 4, 8)
* Programmable Burst type (Sequential & Interleave)
* Edge aligned data output, center aligned data input
* Serial presence detect with EEPROM
* PCB : Height (1,181 mil), double sided component

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