General description
The 74AUP1Z04 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
The 74AUP1Z04 combines the functions of the 74AUP1GU04 and 74AUP1G04 with
enable circuitry and an internal bias resistor to provide a device optimized for use in
crystal oscillator applications.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF at output Y.
The IOFF circuitry disables the output Y, preventing the damaging backflow current through
the device when it is powered down.
When not in use the EN input can be driven HIGH, pulling up the X1 input and putting the
device in a low power disable mode. Schmitt-trigger action at the EN input makes the
circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to
3.6 V.
The integration of the two devices into the 74AUP1Z04 produces the benefits of a
compact footprint, lower power dissipation and stable operation over a wide range of
frequency and temperature.

* Wide supply voltage range from 0.8 V to 3.6 V
* High noise immunity
* ESD protection:
* HBM JESD22-A114D Class 3A exceeds 5000 V
* MM JESD22-A115-A exceeds 200 V
* CDM JESD22-C101C exceeds 1000 V
* Low static power consumption; ICC = 0.9 mA (maximum)
* Latch-up performance exceeds 100 mA per JESD 78 Class II
* Inputs accept voltages up to 3.6 V
* Low noise overshoot and undershoot < 10 % of VCC
* IOFF circuitry provides partial Power-down mode operation at output Y
* Multiple package options
* Specified from -40 °C to +85 °C and -40 °C to +125 °C

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